Datasheet AD9635 (Analog Devices) - 30

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Data Sheet AD9635 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values
Each row in the memory map register table (see Table 16) has After the AD9635 is reset, critical registers are loaded with eight bit locations. The memory map is roughly divided into three default values. The default values for the registers are given in sections: the chip configuration registers (Address 0x00 to Address the memory map register table, Table 16. 0x02); the device index and transfer registers (Address 0x05 and
Logic Levels
Address 0xFF); and the global ADC function registers, including An explanation of logic level terminology follows: setup, control, and test (Address 0x08 to Address 0x102). • The memory map register table lists the default hexadecimal “Bit is set” is synonymous with “bit is set to Logic 1” or value for each hexadecimal address shown. The column with “writing Logic 1 for the bit.” the heading Bit 7 (MSB) is the start of the default hexadecimal • “Clear a bit” is synonymous with “bit is set to Logic 0” or value given. For example, Address 0x05, the device index register, “writing Logic 0 for the bit.” has a hexadecimal default value of 0x33. This means that in
Channel-Specific Registers
Address 0x05, Bits[7:6] = 00, Bits[5:4] = 11, Bits[3:2] = 00, and Some channel setup functions can be programmed differently Bits[1:0] = 11 (in binary). This setting is the default channel for each channel. In these cases, channel address locations are index setting. The default value results in both ADC channels internally duplicated for each channel. These registers and bits receiving the next write command. For more information on are designated in Table 16 as local. These local registers and bits this function and others, see the AN-877 Application Note, can be accessed by setting the appropriate data channel bits (A or Interfacing to High Speed ADCs via SPI. This application note B) and the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in details the functions control ed by Register 0x00 to Register 0xFF. Register 0x05. If all the bits are set, the subsequent write affects The remaining registers are documented in the Memory Map the registers of both channels and the DCO/FCO clock Register Descriptions section. channels. In a read cycle, only one channel (A or B) should be
Open Locations
set to read one of the two registers. If all the bits are set during a All address and bit locations that are not included in Table 16 SPI read cycle, the part returns the value for Channel A. are not currently supported for this device. Unused bits of a Registers and bits that are designated as global in Table 16 affect valid address location should be written with 0s. Writing to these the entire part or the channel features for which independent locations is required only when part of an address location is settings are not al owed between channels. The settings in open (for example, Address 0x05). If the entire address location Register 0x05 do not affect the global registers and bits. is open or not listed in Table 16 (for example, Address 0x13), this address location should not be written. Rev. B | Page 29 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE