Datasheet AD9250 (Analog Devices) - 6

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AD9250 Data Sheet ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p ful -scale input range, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 2. AD9250-170 AD9250-250 Parameter1 Temperature Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 30 MHz 25°C 72.5 72.1 dBFS fIN = 90 MHz 25°C 72.0 71.7 dBFS Full 70.7 dBFS fIN = 140 MHz 25°C 71.4 71.2 dBFS fIN = 185 MHz 25°C 70.7 70.6 dBFS Full 69.3 dBFS fIN = 220 MHz 25°C 70.1 70.0 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz 25°C 71.3 70.7 dBFS fIN = 90 MHz 25°C 70.9 70.5 dBFS Full 69.6 dBFS fIN = 140 MHz 25°C 70.3 70.0 dBFS fIN = 185 MHz 25°C 69.6 69.5 dBFS Full 68.0 dBFS fIN = 220 MHz 25°C 68.9 68.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 11.5 11.5 Bits fIN = 90 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.3 11.3 Bits fIN = 185 MHz 25°C 11.1 11.2 Bits fIN = 220 MHz 25°C 10.9 11.0 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 92 89 dBc fIN = 90 MHz 25°C 95 86 dBc Full 78 dBc fIN = 140 MHz 25°C 91 86 dBc fIN = 185 MHz 25°C 86 88 dBc Full 80 dBc fIN = 220 MHz 25°C 85 88 dBc WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −92 −89 dBc fIN = 90 MHz 25°C −95 −87 dBc Full −78 dBc fIN = 140 MHz 25°C −91 −86 dBc fIN = 185 MHz 25°C −86 −88 dBc Full −80 dBc fIN = 220 MHz 25°C −85 −88 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz 25°C −95 −94 dBc fIN = 90 MHz 25°C −94 −96 dBc Full −78 dBc fIN = 140 MHz 25°C −97 −96 dBc fIN = 185 MHz 25°C −96 −88 dBc Full −80 dBc fIN = 220 MHz 25°C −93 −91 dBc Rev. E | Page 6 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide