Datasheet ADAS3022 (Analog Devices) - 7

FabricanteAnalog Devices
Descripción16-Bit, 1 MSPS, 8 Channel Data Acquisition System
Páginas / Página41 / 7 — ADAS3022. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. …
RevisiónD
Formato / tamaño de archivoPDF / 797 Kb
Idioma del documentoInglés

ADAS3022. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit

ADAS3022 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit

Línea de modelo para esta hoja de datos

Versión de texto del documento

link to page 26 link to page 7
ADAS3022 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
1 IVSSH PGIA gain = 0.16 −3.0 −2.5 mA PGIA gain = 0.2 −3.0 −2.5 mA PGIA gain = 0.4 −3.5 −3.0 mA PGIA gain = 0.8 −5.5 −4.5 mA PGIA gain = 1.6 −9.5 −8.0 mA PGIA gain = 3.2 −17.5 −15 mA PGIA gain = 6.4 −17.5 −15 mA All PGIA gains, PD = 1 10 µA IAVDD PGIA gain = 6.4, reference buffer enabled 18 21.0 mA All other PGIA gains, reference buffer 16 19.0 mA enabled PGIA gain = 6.4, reference buffer disabled 14 17.5 mA All other PGIA gains, reference buffer 12 16.0 mA disabled All PGIA gains, PD = 1 100 µA IDVDD All PGIA gains, PD = 0 2.5 3.5 mA All PGIA gains, PD = 1 10 µA IVIO VIO = 3.3 V, PD = 0 0.30 1.2 mA PD = 1 10 µA Power Supply Sensitivity At TA = 25°C External reference PGIA gain = 0.16, 0.2, 0.4, 0.8; VDDH/VSSH ± 5% ±0.5 LSB PGIA gain = 3.2, VDDH/VSSH ± 5% ±1.0 LSB PGIA gain = 6.4, VDDH/VSSH ± 5% ±2.0 LSB PGIA gain = 0.16, AVDD/DVDD ± 5% ±0.6 LSB PGIA gain = 0.2, AVDD/DVDD ± 5% ±0.8 LSB PGIA gain = 0.4, AVDD/DVDD ± 5% ±1.0 LSB PGIA gain = 0.8, AVDD/DVDD ± 5% ±1.5 LSB PGIA gain = 1.6, AVDD/DVDD ± 5% ±2.0 LSB PGIA gain = 3.2, AVDD/DVDD ± 5% ±3.5 LSB PGIA gain = 6.4, AVDD/DVDD ± 5% ±7.0 LSB TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 LSB means least significant bit and changes depending on the voltage range. See the Programmable Gain section for the LSB size. 2 The common-mode voltage (VCM) range for a PGIA gain of 0.16 or 0.2 is 0 V. 3 All ac accuracy specifications expressed in decibels are referred to a ful -scale input FSR and tested with an input signal at 0.5 dB below ful scale, unless otherwise specified. 4 This is the output from the internal band gap reference. 5 There is no pipeline delay. Conversion results are available immediately after a conversion is complete. 6 The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH − 2.5 V). Rev. C | Page 6 of 40 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview ADAS3022 Operation Transfer Function Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Fully Differential, Antiphase Signals with a Zero Common Mode Fully Differential, Antiphase Signals with a Nonzero Common Mode Differential, Nonantiphase Signals with a Zero Common Mode Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Multiplexer Channel Sequencer Auxiliary Input Channel Driver Amplifier Choice Voltage Reference Output/Input Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising Edge—Start of a Conversion (SOC) BUSY Falling Edge—End of a Conversion (EOC) Reset and Power-Down (PD) Inputs Serial Data Interface CPHA Sampling on the SCK Falling Edge Sampling on the SCK Rising Edge (Alternate Edge) CFG Readback General Considerations Data Access During Conversion—Maximum Throughput General Timing Configuration Register On Demand Conversion Mode Channel Sequencer Details INx and COM Inputs (MUX = 1, TEMPB = 1) INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1) INx and COM Inputs with Temperature Sensor (MUX = 1, TEMPB = 0) INx and COM Inputs with AUX Inputs and Temperature Sensor (MUX = 0, TEMPB = 0) Sequencer Modes Basic Sequencer Mode (SEQ = 11) Update During Sequence (SEQ = 01) Advanced Sequencer Mode (SEQ = 10) Outline Dimensions Ordering Guide