Datasheet AD7175-8 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | 24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
| Páginas / Página | 65 / 4 — Data Sheet. AD7175-8. SPECIFICATIONS. Table 1. Parameter. Test … |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
Data Sheet. AD7175-8. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet AD7175-8 SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥ 125 kSPS 24 Bits Resolution See Table 19 to Table 23 Noise See Table 19 to Table 23 ACCURACY Integral Nonlinearity (INL) All input buffers enabled ±4.5 10 ppm of FSR All input buffers disabled ±1 ±4.5 ppm of FSR Offset Error2 Internal short ±60 µV Offset Drift Internal short ±150 nV/°C Gain Error2 ±80 ±110 ppm of FSR Gain Drift1 ±0.5 ±0.75 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, for V = 1 V 90 dB IN Common-Mode Rejection V = 0.1 V IN At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (post filter), 50 Hz ± 120 dB 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range V = (REF+) − (REF−) ±V V REF REF Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock ±4 nA/V/°C Input Buffers Enabled Input Current ±30 nA Input Current Drift AVDD1 − 0.2 V to AVSS + 0.2 V ±75 pA/°C AVDD1 to AVSS ±1 nA/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT, with respect to AVSS 2.5 V Initial Accuracy3 REFOUT, T = 25°C A −0.12 +0.12 % of V Temperature Coefficient1 0°C to 105°C ±2 ±5 ppm/°C −40°C to +105°C ±3 ±10 ppm/°C Reference Load Current, I −10 +10 mA LOAD Power Supply Rejection AVDD1, AVDD2 (line regulation) 95 dB Load Regulation ∆V /∆I OUT LOAD 32 ppm/mA Voltage Noise e , 0.1 Hz to 10 Hz, 2.5 V reference 4.5 µV rms N Voltage Noise Density e , 1 kHz, 2.5 V reference 215 nV/√Hz N Rev. 0 | Page 3 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7175-8 SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥ 125 kSPS 24 Bits Resolution See Table 19 to Table 23 Noise See Table 19 to Table 23 ACCURACY Integral Nonlinearity (INL) All input buffers enabled ±4.5 10 ppm of FSR All input buffers disabled ±1 ±4.5 ppm of FSR Offset Error2 Internal short ±60 µV Offset Drift Internal short ±150 nV/°C Gain Error2 ±80 ±110 ppm of FSR Gain Drift1 ±0.5 ±0.75 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, for V = 1 V 90 dB IN Common-Mode Rejection V = 0.1 V IN At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (post filter), 50 Hz ± 120 dB 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range V = (REF+) − (REF−) ±V V REF REF Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock ±4 nA/V/°C Input Buffers Enabled Input Current ±30 nA Input Current Drift AVDD1 − 0.2 V to AVSS + 0.2 V ±75 pA/°C AVDD1 to AVSS ±1 nA/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT, with respect to AVSS 2.5 V Initial Accuracy3 REFOUT, T = 25°C A −0.12 +0.12 % of V Temperature Coefficient1 0°C to 105°C ±2 ±5 ppm/°C −40°C to +105°C ±3 ±10 ppm/°C Reference Load Current, I −10 +10 mA LOAD Power Supply Rejection AVDD1, AVDD2 (line regulation) 95 dB Load Regulation ∆V /∆I OUT LOAD 32 ppm/mA Voltage Noise e , 0.1 Hz to 10 Hz, 2.5 V reference 4.5 µV rms N Voltage Noise Density e , 1 kHz, 2.5 V reference 215 nV/√Hz N Rev. 0 | Page 3 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE