Datasheet ADAS3023 (Analog Devices) - 9

ADAS3023 Data Sheet Timing Diagrams SOC SOC SOC tCYC EOC EOC POWER tCONV UP NOTE 1 NOTE 2 NOTE 1 PHASE CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) ACQUISITION (n + 2) CNV tCNVH NOTE 4 tAD CS NOTE 3 1 16 1 16 1 16 1 16 1 16 1 16 SCK NOTE 2 DIN CFG (n + 2) CFG (n + 3) SDO CH0 CH1 CH7 CH0 CH1 CH7 BUSY/ SDO2 tCBD DATA (n) DATA (n + 1) NOTES 1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC). 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED WITH CONVERSION.
004
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL. 4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, tAD, SHOULD LAPSE PRIOR TO DATA ACCESS.
10942- Figure 4. General Timing Diagram with BUSY/SDO2 Disabled
SOC SOC SOC tCYC EOC EOC POWER tCONV UP NOTE 1 NOTE 1 PHASE CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) ACQUISITION (n + 2) CNV tCNVH NOTE 4 tAD CS NOTE 3 1 16 1 16 1 16 1 16 1 16 1 16 1 16 1 16 SCK NOTE 2 DIN CFG (n + 2) CFG (n + 3) SDO CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 BUSY/ SDO2 CH4 CH5 CH6 CH7 CH4 CH5 CH6 CH7 DATA (n) DATA (n + 1) NOTES 1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC). 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED WITH CONVERSION.
005
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL. 4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, tAD, SHOULD LAPSE PRIOR TO DATA ACCESS.
10942- Figure 5. General Timing Diagram with BUSY/SDO2 Enabled Rev. A | Page 8 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide