Datasheet ADAS3023 (Analog Devices) - 4

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Data Sheet ADAS3023 SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%; VIO = 1.8 V to AVDD, Internal Reference VREF = 4.096 V, fS = 500 kSPS, all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit1
RESOLUTION 16 Bits ANALOG INPUT (IN0 to IN7, COM) Input Impedance ZIN 500 MΩ Operating Input Voltage Range2 VIN, on any single pin VSSH + 2.5 VDDH − 2.5 V Differential Input Voltage Ranges, VIN VINX − COM PGIA gain = 0.2, VIN = 40.96 V p-p −5VREF +5VREF V PGIA gain = 0.4, VIN = 20.48 V p-p −2.5VREF +2.5VREF V PGIA gain = 0.8, VIN = 10.24 V p-p −1.25VREF +1.25VREF V PGIA gain = 1.6, VIN = 5.12 V p-p −0.625VREF +0.625VREF V THROUGHPUT Conversion Rate Two channels 0 500 kSPS Four channels 0 250 kSPS Six channels 0 167 kSPS Eight channels 0 125 kSPS Transient Response3 Full-scale step 820 ns DC ACCURACY No Missing Codes 16 Bits Integral Linearity Error PGIA gain = 0.2, 0.4, or 0.8, COM = 0 V −2.5 ±1 +2.5 LSB PGIA gain = 1.6, COM = 0 V −3 ±1 +3 Differential Linearity Error All PGIA gains, COM = 0 V −0.95 ±0.5 +1.25 LSB Transition Noise PGIA gain = 0.2 or 0.4 6 LSB PGIA gain = 0.8 7 LSB PGIA gain = 1.6 10 LSB Gain Error4 External reference, all PGIA gains −0.075 +0.075 %FS Gain Error Match, Delta Mean External reference, all PGIA gains −0.05 +0.05 %FS Gain Error Temperature Drift External reference, PGIA gain = 0.2, 0.4, or 0.8 1 ppm/°C External reference, PGIA gain = 1.6 2 ppm/°C Offset Error4 External reference, PGIA gain = 0.2 −65 −35 +12 LSB External reference, PGIA gain = 0.4 −85 −45 +12 LSB External reference, PGIA gain = 0.8 −10 0 +10 LSB External reference, PGIA gain = 1.6 0 130 250 LSB Offset Error Match, Delta Mean External reference, PGIA gain = 0.2, 0.4, 0.8, or 1.6 −15 ±1 +15 LSB Offset Error Temperature Drift External reference, PGIA gain = 0.2 or 0.4, IN0 to IN7 0 0.5 2 ppm/°C External reference, PGIA gain = 0.8, IN0 to IN7 0 1.5 3 ppm/°C External reference, PGIA gain = 1.6, IN0 to IN7 0 2.5 5 ppm/°C AC ACCURACY5 Internal reference Signal-to-Noise Ratio fIN = 1 kHz, COM = 0 V PGIA gain = 0.2 90.0 91.5 dB PGIA gain = 0.4 89.5 91.0 dB PGIA gain = 0.8 87.5 89.0 dB PGIA gain = 1.6 85.0 86.5 dB Signal-to-Noise + Distortion (SINAD) fIN = 1 kHz, two, four, six, and eight channels PGIA gain = 0.2 89.5 91.0 dB PGIA gain = 0.4 89.0 90.5 dB PGIA gain = 0.8 87.0 88.5 dB PGIA gain = 1.6 84.0 86.0 dB Rev. A | Page 3 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide