Datasheet AD7173-8 (Analog Devices) - 9

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Data Sheet AD7173-8 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE Table 3.
θJA is specified for a device soldered on a JEDEC test board for
Parameter Rating
surface-mount packages. The values listed in Table 4 are based AVDD1, AVDD2 to AVSS −0.3 V to +6.5 V on simulated data. AVDD1 to DGND −0.3 V to +6.5 V
Table 4. Thermal Resistance
IOVDD to DGND −0.3 V to +6.5 V
Package Type θ Unit JA
IOVDD to AVSS −0.3 V to +7.5 V 40-Lead, 6 mm × 6 mm LFCSP AVSS to DGND −3.25 V to +0.3 V 1-Layer JEDEC Board 114 °C/W Analog Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V 4-Layer JEDEC Board 54 °C/W Reference Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V 4-Layer JEDEC Board with 16 Thermal Vias 34 °C/W Digital Input Voltage to DGND −0.3 V to IOVDD + 0.3 V Digital Output Voltage to DGND −0.3 V to IOVDD + 0.3 V AIN[16:0] or Digital Input Current 10 mA
ESD CAUTION
Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Soldering, Reflow Temperature 260°C ESD Rating (HBM) 4 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 9 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES