Datasheet AD7091R-2, AD7091R-4, AD7091R-8 (Analog Devices) - 8

AD7091R-2/AD7091R-4/AD7091R-8 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS T T S E IV NV ESE DR R CS V CO 61 51 41 31 VDD 1 12 SCLK SDO CS REGCAP 2 11 1 16 V AD7091R-2 DRIVE REF 3 TOP VIEW 10 SDI RESET 2 15 CONVST IN/REFOUT (Not to Scale) GND 4 9 GND V 3 14 DD SCLK REGCAP 4 AD7091R-2 13 SDO 5 6 7 8 TOP VIEW REF T 0 1 IN/REFOUT 5 12 (Not to Scale) SDI IN IN IN OU C V V X GND 6 11 GND AD MU MUXOUT 7 10 ADCIN NOTES 1. THE EXPOSED PAD IS NOT CONNECTED
08
V 8 9
007 0
IN0 VIN1 INTERNALLY. IT IS RECOMMENDED THAT
891- 10
THE PAD BE SOLDERED TO GND.
0891- 1 Figure 5. 2-Channel, 16-Lead TSSOP Pin Configuration Figure 6. 2-Channel, 16-Lead LFCSP Pin Configuration
Table 5. 2-Channel, 16-Lead LFCSP and 16-Lead TSSOP Pin Function Descriptions Pin No. T Mnemonic Description SSOP LFCSP
1 15 CS Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on the SPI. 2 16 RESET Reset. Logic input. 3 1 VDD Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND. 4 2 REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin separately to GND using a 1.0 μF capacitor. 5 3 REFIN/REFOUT Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the internal reference with the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.0 V to VDD. 6, 11 4, 9 GND Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-2. 7 5 MUXOUT Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to the ADCIN pin. 8 6 VIN0 Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF. 9 7 VIN1 Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF. 10 8 ADCIN ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is required, tie this pin directly to the MUXOUT pin; otherwise tie the input of the conditioning network to the MUXOUT pin. 12 10 SDI Serial Data Input Bus. This input provides the data written to the on-chip control registers. Data clocks into the registers on the falling edge of the SCLK input. Provide data MSBs first. 13 11 SDO Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are required to access the data. The data is provided MSB first. 14 12 SCLK Serial Clock. This pin acts as the serial clock input. 15 13 CONVST Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track- and-hold mode into hold mode and initiates a conversion. 16 14 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Connect decoupling capacitors between VDRIVE and GND. Typical recommended values are 10 μF and 0.1 μF. The voltage range on this pin is 1.8 V to 5.25 V and may be different to the voltage range at VDD. Not 17 EPAD Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be applicable soldered to GND. Rev. C | Page 8 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION REFERENCE POWER SUPPLY DEVICE RESET TYPICAL CONNECTION DIAGRAM ANALOG INPUT DRIVER AMPLIFIER CHOICE REGISTERS ADDRESSING REGISTERS CONVERSION RESULT REGISTER CHANNEL REGISTER CONFIGURATION REGISTER ALERT INDICATION REGISTER CHANNEL x LOW LIMIT REGISTER CHANNEL x HIGH LIMIT REGISTER CHANNEL x HYSTERESIS REGISTER SERIAL PORT INTERFACE READING CONVERSION RESULT WRITING DATA TO THE REGISTERS READING DATA FROM THE REGISTERS POWER-ON DEVICE INITIALIZATION MODES OF OPERATION NORMAL MODE POWER-DOWN MODE ALERT (AD7091R-4 AND AD7091R-8 ONLY) BUSY (AD7091R-4 AND AD7091R-8 ONLY) CHANNEL SEQUENCER DAISY CHAIN OUTLINE DIMENSIONS ORDERING GUIDE