Datasheet AD9652 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 16-bit, 310 MSPS, 3.3/1.8 V Dual Analog-to-Digital Converter (ADC) |
| Páginas / Página | 37 / 9 — AD9652. Data Sheet. Timing Diagrams. N – 1. N + 4. N + 5. N + 3. VIN±x. N … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 1.5 Mb |
| Idioma del documento | Inglés |
AD9652. Data Sheet. Timing Diagrams. N – 1. N + 4. N + 5. N + 3. VIN±x. N + 1. N + 2. tCH. tCLK. CLK+. CLK–. tDCO. DCO–. DCO+. tSKEW. tPD
Línea de modelo para esta hoja de datos
Versión de texto del documento
AD9652 Data Sheet Timing Diagrams tA N – 1 N + 4 N + 5 N N + 3 VIN±x N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO– DCO+ tSKEW tPD PARALLEL INTERLEAVED CH A CH B CH A CH B CH A CH B CH A CH B CH A D0± (LSB) N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22 CHANNEL A AND CHANNEL B CH A CH B CH A CH B CH A CH B CH A CH B CH A
002
D15± (MSB) N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
12169- Figure 2. LVDS Data Output Timing
CLK± tSSYNC tHSYNC
003
SYNC
12169- Figure 3. SYNC Timing Inputs
t t HIGH DS tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
049
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
12169- Figure 4. Serial Port Interface Timing Diagram Rev. B | Page 8 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide
002
D15± (MSB) N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
12169- Figure 2. LVDS Data Output Timing
CLK± tSSYNC tHSYNC
003
SYNC
12169- Figure 3. SYNC Timing Inputs
t t HIGH DS tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
049
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
12169- Figure 4. Serial Port Interface Timing Diagram Rev. B | Page 8 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide