Datasheet AD9652 (Analog Devices) - 7

AD9652 Data Sheet Parameter Test Conditions/Comments Temperature Min Typ Max Unit
LOGIC INPUT (CSB)2 High Level Input Voltage Full 1.22 SPIVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −65 +65 µA Low Level Input Current Full −135 0 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK)3 High Level Input Voltage Full 1.22 SPIVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 0 110 µA Low Level Input Current Full −60 +50 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO)2 High Level Input Voltage Full 1.22 SPIVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −65 +70 µA Low Level Input Current Full −135 0 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF LOGIC INPUTS (PDWN)3 High Level Input Voltage Full 1.22 DRVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −80 +190 µA Low Level Input Current Full −145 +130 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS LVDS Data and OR± Outputs Assumes nominal 100 Ω differential termination ANSI Mode Differential Output Voltage (VOD) Maximum setting, default Full 310 350 450 mV Output Offset Voltage (VOS) Full 1.15 1.22 1.35 V Reduced Swing Mode Differential Output Voltage (VOD) Minimum setting Full 150 200 280 mV Output Offset Voltage (VOS) Full 1.15 1.22 1.35 V 1 Input capacitance/resistance refers to the effective capacitance/resistance between one differential input pin and AGND. 2 Internal weak pull-up. 3 Internal weak pull-down. Rev. B | Page 6 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide