Datasheet AD7172-2 (Analog Devices) - 3

FabricanteAnalog Devices
DescripciónLow Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers
Páginas / Página61 / 3 — AD7172-2. Data Sheet. TABLE OF CONTENTS
RevisiónA
Formato / tamaño de archivoPDF / 1.1 Mb
Idioma del documentoInglés

AD7172-2. Data Sheet. TABLE OF CONTENTS

AD7172-2 Data Sheet TABLE OF CONTENTS

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AD7172-2 Data Sheet TABLE OF CONTENTS
Features .. 1 CRC Calculation ... 42 Applications ... 1 Integrated Functions .. 44 General Description ... 1 General-Purpose Input/Output.. 44 Functional Block Diagram .. 1 External Multiplexer Control ... 44 Revision History ... 3 Delay .. 44 Specifications ... 4 16-Bit/24-Bit Conversions... 44 Timing Characteristics .. 7 DOUT_RESET ... 44 Timing Diagrams .. 8 Synchronization .. 44 Absolute Maximum Ratings .. 9 Error Flags ... 45 Thermal Resistance .. 9 DATA_STAT ... 45 ESD Caution .. 9 IOSTRENGTH ... 46 Pin Configuration and Function Descriptions ... 10 Internal Temperature Sensor .. 46 Typical Performance Characteristics ... 12 Grounding and Layout .. 47 Noise Performance and Resolution .. 19 Register Summary .. 48 Getting Started .. 20 Register Details ... 49 Power Supplies .. 21 Communications Register ... 49 Digital Communication ... 21 Status Register ... 50 AD7172-2 Reset .. 22 ADC Mode Register ... 51 Configuration Overview ... 22 Interface Mode Register .. 52 Circuit Description ... 27 Register Check .. 53 Buffered Analog Input ... 27 Data Register ... 53 Crosspoint Multiplexer .. 27 GPIO Configuration Register ... 54 AD7172-2 Reference .. 28 ID Register... 55 Buffered Reference Input ... 29 Channel Register 0 ... 55 Clock Source ... 29 Channel Register 1 to Channel Register 3 .. 56 Digital Filters ... 30 Setup Configuration Register 0 .. 57 Sinc5 + Sinc1 Filter ... 30 Setup Configuration Register 1 to Setup Configuration Sinc3 Filter ... 30 Register 3 ... 57 Single Cycle Settling ... 31 Filter Configuration Register 0 ... 58 Enhanced 50 Hz and 60 Hz Rejection Filters ... 34 Filter Configuration Register 1 to Filter Configuration Register 3 ... 59 Operating Modes .. 37 Offset Register 0 ... 59 Continuous Conversion Mode ... 37 Offset Register 1 to Offset Register 3 ... 59 Continuous Read Mode ... 38 Gain Register 0.. 59 Single Conversion Mode ... 39 Gain Register 1 to Gain Register 3 ... 59 Standby and Power-Down Modes .. 40 Outline Dimensions ... 60 Calibration ... 40 Ordering Guide .. 60 Digital Interface .. 41 Checksum Protection... 41 Rev. A | Page 2 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE