Datasheet AD7124-8 (Analog Devices) - 10

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Data Sheet AD7124-8 Parameter1 Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS (INCLUDING CLK) Output Voltage2 High, VOH IOVDD − 0.35 V ISOURCE = 100 µA Low, VOL 0.4 V ISINK = 100 µA Floating State Leakage Current −1 +1 µA Floating State Output Capacitance 10 pF Data Output Coding Offset binary SYSTEM CALIBRATION2 Calibration Limit Full-Scale 1.05 × FS V Zero-Scale −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER SUPPLY VOLTAGES FOR ALL POWER MODES AVDD to AVSS Low Power Mode 2.7 3.6 V Mid Power Mode 2.7 3.6 V Full Power Mode 2.9 3.6 V IOVDD to GND 1.65 3.6 V AVSS to GND −1.8 0 V IOVDD to AVSS 5.4 V POWER SUPPLY CURRENTS11, 13 IAVDD, External Reference Low Power Mode Gain = 12 125 140 µA All buffers off Gain = 1 IAVDD Increase per AINx Buffer2 15 25 µA Gain = 2 to 8 205 250 µA Gain = 16 to 128 235 300 µA IAVDD Increase per Reference Buffer2 10 20 µA All gains Mid Power Mode Gain = 12 150 170 µA All buffers off Gain = 1 IAVDD Increase per AINx Buffer2 30 40 µA Gain = 2 to 8 275 345 µA Gain = 16 to 128 330 430 µA IAVDD Increase per Reference Buffer2 20 30 µA All gains Full Power Mode Gain = 12 315 350 µA All buffers off Gain = 1 IAVDD Increase per AINx Buffer2 90 135 µA Gain = 2 to 8 660 830 µA Gain = 16 to 128 875 1200 µA IAVDD Increase per Reference Buffer2 85 120 µA All gains IAVDD Increase Due to Internal Reference2 50 70 µA Independent of power mode; the reference buffers are not required when using this reference Due to V 2 BIAS 15 20 µA Independent of power mode Due to Diagnostics2 4 5 µA IIOVDD Low Power Mode 20 35 µA Mid Power Mode 25 40 µA Full Power Mode 55 80 µA Rev. D | Page 9 of 92 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE