Data SheetAD7915/AD7916PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSREF 110 VIOVDD 2AD7915/9SDI/CSIN+ 3AD79168SCKTOP VIEWIN– 4REF7SDO110 VIO(Not to Scale)VDDGND 52AD7915/9 SDI/CS6CNVAD7916IN+ 38 SCKTOP VIEWIN– 47 SDONOTES(Not to Scale)1. THE EXPOSED PAD CAN BE CONNECTED TO GND. -004 005 GND 56 CNVTHIS CONNECTION IS NOT REQUIRED TO MEET 83- 12583 THE ELECTRICAL PERFORMANCES. 125 Figure 3. 10-Lead MSOP Pin Configuration Figure 4. 10-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No.MnemonicType1 Description 1 REF AI Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Conversion Input. This input has multiple functions. On its leading edge, CNV initiates the conversions and selects the interface mode of the device: chain mode or chip select (CS) mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 9 SDI/CS DI Serial Data Input/Chip Select. This input has multiple functions. It selects the interface mode of the ADC as follows: Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI/CS is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI/CS is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI/CS is high during the CNV rising edge. In this mode, either SDI/CS or CNV can enable the serial output signals when low. 10 VIO P Input/Output Interface Digital Power. This pin is nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EP Exposed Pad. For the lead frame chip scale package (LFCSP), the exposed pad can be connected to GND. This connection is not required to meet the electrical performances. 1AI is analog input, P is power, DI is digital input, and DO is digital output. Rev. 0 | Page 7 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATIONS CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE SINGLE TO DIFFERENTIAL DRIVER VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE MODE, 3-WIRE, WITHOUT BUSY INDICATOR MODE 3-WIRE, WITH BUSY INDICATOR MODE, 4-WIRE, WITHOUT BUSY INDICATOR MODE 4-WIRE WITH BUSY INDICATOR CHAIN MODE, WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATIONS INFORMATION INTERFACING TO BLACKFIN DSP LAYOUT EVALUATING AD7915/AD7916 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES