Datasheet AD7172-4 (Analog Devices) - 3

FabricanteAnalog Devices
DescripciónLow Power, with 4- or 8-channel, 24-bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers
Páginas / Página62 / 3 — AD7172-4. Data Sheet. TABLE OF CONTENTS
RevisiónB
Formato / tamaño de archivoPDF / 862 Kb
Idioma del documentoInglés

AD7172-4. Data Sheet. TABLE OF CONTENTS

AD7172-4 Data Sheet TABLE OF CONTENTS

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AD7172-4 Data Sheet TABLE OF CONTENTS
Features .. 1  CRC Calculation ... 40  Applications ... 1  Integrated Functions .. 42  General Description ... 1  General-Purpose Input/Output.. 42  Functional Block Diagram .. 1  External Multiplexer Control ... 42  Revision History ... 3  Delay .. 42  Specifications ... 4  16-Bit/24-Bit Conversions ... 42  Timing Characteristics .. 7  DOUT_RESET ... 42  Timing Diagrams .. 7  Synchronization .. 42  Absolute Maximum Ratings .. 8  Error Flags ... 43  Thermal Resistance .. 8  DATA_STAT ... 43  ESD Caution .. 8  IOSTRENGTH ... 43  Pin Configuration and Function Descriptions ... 9  Grounding and Layout .. 44  Typical Performance Characteristics ... 11  Register Summary .. 45  Noise Performance and Resolution .. 17  Register Details ... 47  Getting Started .. 18  Communications Register ... 47  Power Supplies .. 19  Status Register ... 48  Digital Communication ... 19  ADC Mode Register ... 49  AD7172-4 Reset .. 20  Interface Mode Register .. 50  Configuration Overview ... 20  Register Check .. 51  Circuit Description ... 26  Data Register ... 51  Buffered Analog Input ... 26  GPIO Configuration Register ... 52  Crosspoint Multiplexer .. 26  ID Register... 53  AD7172-4 Reference .. 27  Channel Register 0 ... 54  Buffered Reference Input ... 28  Channel Register 1 to Channel Register 7 .. 55  Clock Source ... 28  Setup Configuration Register 0 .. 56  Digital Filters ... 29  Setup Configuration Register 1 to Setup Configuration Sinc5 + Sinc1 Filter ... 29  Register 7 ... 57  Sinc3 Filter ... 29  Filter Configuration Register 0 ... 58  Single Cycle Settling ... 30  Filter Configuration Register 1 to Filter Configuration Register 7 ... 59  Enhanced 50 Hz and 60 Hz Rejection Filters ... 33  Offset Register 0 ... 59  Operating Modes .. 35  Offset Register 1 to Offset Register 7 ... 59  Continuous Conversion Mode ... 35  Gain Register 0.. 60  Continuous Read Mode ... 36  Gain Register 1 to Gain Register 7 ... 60  Single Conversion Mode ... 37  Outline Dimensions ... 61  Standby and Power-Down Modes .. 38  Ordering Guide .. 61  Calibration ... 38  Digital Interface .. 39  Checksum Protection ... 39  Rev. B | Page 2 of 61 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-4 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-4 REFERENCE BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 7 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE