Datasheet AD7761 (Analog Devices) - 8

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Data Sheet AD7761 Parameter Test Conditions/Comments Min Typ Max Unit
LVDS Clock2 RL = 100 Ω Differential Input Voltage 100 650 mV Common-Mode Input Voltage 800 1575 mV Absolute Input Voltage 1.88 V ADC RESET2 ADC Start-Up Time After Reset6 Time to first DRDY, fast mode, 1.58 1.66 ms decimation by 32 Minimum RESET Low Pulse Width tMCLK = 1/MCLK 2 × tMCLK LOGIC INPUTS Input Voltage2 High, VINH 0.65 × V IOVDD Low, VINL 2.25 V < IOVDD < 3.6 V 0.7 V 1.72 V < IOVDD < 1.88 V 0.4 V Hysteresis2 2.25 V < IOVDD < 3.6 V 0.04 0.09 V 1.72 V < IOVDD < 1.88 V 0.04 0.2 V Leakage Current −10 +0.03 +10 µA RESET pin7 −10 +10 µA LOGIC OUTPUTS Output Voltage2 High, VOH ISOURCE = 200 μA 0.8 × V IOVDD Low, VOL ISINK = 400 µA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × VREF V Zero-Scale Calibration Limit −1.05 × V VREF Input Span 0.4 × VREF 2.1 × VREF V POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS 4.5 5.0 5.5 V AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V AVSS − DGND −2.75 0 V IOVDD − DGND 1.72 2.5 to 3.3 3.6 V or 1.8 POWER SUPPLY CURRENTS Maximum output data rate, CMOS MCLK, eight DOUTx signals, all supplies at maximum voltages, all channels in Channel Mode A Eight Channels Active Fast Mode AVDD1 Current Precharge reference buffers off 36 40 mA Precharge reference buffers on 57.5 64 mA AVDD2 Current 37.5 40 mA IOVDD Current Wideband filter 63 69 mA Sinc5 filter2 27 29 mA Median Mode AVDD1 Current Precharge reference buffers off 18.5 mA Precharge reference buffers on 29 mA AVDD2 Current 21.3 mA IOVDD Current Wideband filter 34 mA Sinc5 filter 16 mA Rev. A | Page 7 of 75 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE