Datasheet AD7761 (Analog Devices) - 5

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AD7761 Data Sheet GENERAL DESCRIPTION
The AD7761 is an 8-channel, simultaneous sampling sigma-delta The wideband and sinc5 filters can be selected and run on a per (Σ-Δ) analog-to-digital converter (ADC) with a Σ-Δ modulator channel basis. and digital filter per channel, enabling synchronized sampling of ac Within these filter options, the user can improve the dynamic and dc signals. range by selecting from decimation rates of ×32, ×64, ×128, The AD7761 achieves 97.7 dB dynamic range at a maximum ×256, ×512, and ×1024. The ability to vary the decimation input bandwidth of 110.8 kHz, combined with typical performance filtering optimizes noise performance to the required input of ±1 LSB integral nonlinearity (INL), ±1 LSB offset error, and bandwidth. ±5 LSB gain error. Embedded analog functionality on each ADC channel makes The AD7761 user can trade off input bandwidth, output data rate, design easier, such as a precharge buffer on each analog input and power dissipation. Select one of three power modes to optimize that reduces analog input current and a precharge reference the device for noise targets and power consumption. The buffer per channel reduces input current and glitches on the flexibility of the AD7761 allows it to become a reusable platform reference input terminals. for low power dc and high performance ac measurement The device operates with a 5 V AVDD1A and AVDD1B supply, modules. a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to The AD7761 has three modes: fast mode (256 kSPS maximum, 3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation 110.8 kHz input bandwidth, 51.5 mW per channel), median section for specific requirements for operating at 1.8 V IOVDD). mode (128 kSPS maximum, 55.4 kHz input bandwidth, 27.5 mW The device requires an external reference; the absolute input per channel) and low power mode (32 kSPS maximum, 13.8 kHz reference voltage range is 1 V to AVDD1 − AVSS. input bandwidth, 9.375 mW per channel). For the purposes of clarity within this data sheet, the AVDD1A The AD7761 offers extensive digital filtering capabilities, such as and AVDD1B supplies are referred to as AVDD1 and the AVDD2A a wideband, low ±0.005 dB pass-band ripple, antialiasing low- and AVDD2B supplies are referred to as AVDD2. For the pass filter with sharp roll-off, and 105 dB attenuation at the negative supplies, AVSS refers to the AVSS1A, AVSS1B, Nyquist frequency. AVSS2A, AVSS2B, and AVSS pins. Frequency domain measurements can use the wideband linear The specified operating temperature range is −40°C to +105°C. phase filter. This filter has a flat pass band (±0.005 dB ripple) The device is housed in a 10 mm × 10 mm 64-lead LQFP package from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at with a 12 mm × 12 mm printed circuit board (PCB) footprint. 128 kSPS, or from dc to 12.8 kHz at 32 kSPS. Throughout this data sheet, multifunction pins, such as The AD7761 also offers sinc response via a sinc5 filter, a low XTAL2/MCLK, are referred to either by the entire pin name or latency path for low bandwidth, and low noise measurements. by a single function of the pin, for example MCLK, when only that function is relevant. Rev. A | Page 4 of 75 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE