Datasheet AD7768, AD7768-4 (Analog Devices) - 9

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Data Sheet AD7768/AD7768-4 Parameter Test Conditions/Comments Min Typ Max Unit
Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × VREF V Zero-Scale Calibration Limit −1.05 × VREF V Input Span 0.4 × VREF 2.1 × VREF V POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS 4.5 5.0 5.5 V AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V AVSS − DGND −2.75 0 V IOVDD − DGND See Table 2 for 1.8 V operation 2.25 2.5 to 3.3 3.6 V POWER SUPPLY CURRENTS Maximum output data rate, CMOS MCLK, eight DOUTx signals, all supplies at maximum voltages, all channels in Channel Mode A except where otherwise specified AD7768 Eight channels active Fast Mode AVDD1 Current Reference precharge buffers off/on 36/57.5 40/64 mA AVDD2 Current 37.5 40 mA IOVDD Current Wideband filter 63 67 mA Sinc5 filter 27 29 mA Median Mode AVDD1 Current Reference precharge buffers off/on 18.5/29 20.5/32.5 mA AVDD2 Current 21.3 23 mA IOVDD Current Wideband filter 34 37 mA Sinc5 filter 16 18 mA Eco Mode AVDD1 Current Reference precharge buffers off/on 5.1/8 5.8/9 mA AVDD2 Current 9.3 10.1 mA IOVDD Current Wideband filter 12.5 13.7 mA Sinc5 filter 8 9 mA AD7768-4 Four Channels Active Fast Mode AVDD1 Current Reference precharge buffers off/on 18.2/28.8 20.3/32.5 mA AVDD2 Current 18.8 20.3 mA IOVDD Current Wideband filter2 43.5 46.8 mA Wideband filter, SPI mode only; 37 40 mA Channel Mode A set to sinc5 filter8 Sinc5 filter2 17 18.6 mA Median Mode AVDD1 Current Reference precharge buffers off/on 9.3/14.7 10.5/16.6 mA AVDD2 Current 10.7 11.7 mA IOVDD Current Wideband filter2 24.4 26.4 mA Wideband filter, SPI mode only; 21 23 mA Channel Mode A set to sinc5 filter8 Sinc5 filter2 11 12.3 mA Eco Mode AVDD1 Current Reference precharge buffers off/on 2.7/4.1 3.1/4.7 mA AVDD2 Current 4.7 5.3 mA Rev. A | Page 9 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE