Datasheet AD7768, AD7768-4 (Analog Devices) - 6

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AD7768/AD7768-4 Data Sheet SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 2.25 V to 3.6 V, AVSS = DGND = 0 V, REFx+ = 4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, wideband filter, fCHOP = fMOD/32, TA = −40°C to +105°C, unless otherwise noted. See Table 2 for specifications at 1.8 V IOVDD.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR), per Fast 8 256 kSPS Channel1 Median 4 128 kSPS Eco 1 32 kSPS −3 dB Bandwidth Fast, wideband filter 110.8 kHz Median, wideband filter 55.4 kHz Eco, wideband filter 13.8 kHz Data Output Coding Twos complement, MSB first No Missing Codes2 24 Bits DYNAMIC PERFORMANCE For 1.8 V operation, see Table 2; for dynamic range and SNR across all dec- imation rates, see Table 12 and Table 13 Fast Decimation by 32, 256 kSPS ODR Dynamic Range Shorted input, wideband filter 106.2 108 dB Signal-to-Noise Ratio (SNR) 1 kHz, −0.5 dBFS, sine wave input Sinc5 filter 109 111 dB Wideband filter 106 107.8 dB Signal-to-Noise-and- 1 kHz, −0.5 dBFS, sine wave input 104.7 107.5 dB Distortion Ratio (SINAD) Total Harmonic Distortion 1 kHz, −0.5 dBFS, sine wave input −120 −107 dB (THD) Spurious-Free Dynamic 128 dBc Range (SFDR) Median Decimation by 32, 128 kHz ODR Dynamic Range Shorted input, wideband filter 106.2 108 dB SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave 109 111 dB input Wideband filter, 1 kHz, −0.5 dBFS, sine 106 107.8 dB wave input SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB SFDR 128 dBc Eco Decimation by 32, 32 kHz ODR Dynamic Range Shorted input, wideband filter 106.2 108 dB SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave 109 111 dB input Wideband filter, 1 kHz, −0.5 dBFS, sine 106 107.8 dB wave input SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB SFDR 128 dBc INTERMODULATON DISTORTION fa = 9.7 kHz, fb = 10.3 kHz (IMD)3 Second order −125 dB Third order −125 dB Rev. A | Page 6 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE