Datasheet AD9694 (Analog Devices) - 6

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Data Sheet AD9694 AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 2. 500 MSPS AC Specifications Analog Input Full Scale = Analog Input Full Scale = Analog Input Full Scale = 1.44 V p-p 1.80 V p-p 2.16 V p-p Parameter1 Min Typ Max Min Typ Max Min Typ Max Unit
ANALOG INPUT FULL SCALE 1.44 1.80 2.16 V p-p NOISE DENSITY2 −149.7 −151.5 −153.0 dBFS/Hz SIGNAL-TO-NOISE RATIO (SNR)3 fIN = 10 MHz 65.4 67.1 68.4 dBFS fIN = 155 MHz 65.3 64.8 67.0 68.3 dBFS fIN = 305 MHz 65.2 66.8 68.0 dBFS fIN = 450 MHz 65.0 66.6 67.8 dBFS fIN = 765 MHz 64.8 66.5 67.5 dBFS fIN = 985 MHz 64.5 66.0 66.9 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)2 fIN = 10 MHz 65.3 67.0 68.2 dBFS fIN = 155 MHz 65.2 64.5 66.8 67.9 dBFS fIN = 305 MHz 65.1 66.6 67.6 dBFS fIN = 450 MHz 65.0 66.4 67.3 dBFS fIN = 765 MHz 64.7 66.1 66.9 dBFS fIN = 985 MHz 64.2 65.5 66.2 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 10.5 10.8 11.0 Bits fIN = 155 MHz 10.5 10.4 10.8 10.9 Bits fIN = 305 MHz 10.5 10.7 10.9 Bits fIN = 450 MHz 10.5 10.7 10.8 Bits fIN = 765 MHz 10.4 10.6 10.8 Bits fIN = 985 MHz 10.3 10.6 10.7 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) 2 fIN = 10 MHz 89 90 80 dBFS fIN = 155 MHz 89 75 85 77 dBFS fIN = 305 MHz 82 82 78 dBFS fIN = 450 MHz 82 83 77 dBFS fIN = 765 MHz 77 75 72 dBFS fIN = 985 MHz 82 79 76 dBFS SPURIOUS-FREE DYNAMIC RANGE (SFDR) AT −3 dBFS fIN = 10 MHz 94 94 86 dBFS fIN = 155 MHz 94 90 82 dBFS fIN = 305 MHz 89 90 83 dBFS fIN = 450 MHz 87 86 84 dBFS fIN = 765 MHz 82 80 77 dBFS fIN = 985 MHz 85 82 79 dBFS WORST HARMONIC, SECOND OR THIRD2 fIN = 10 MHz −89 −90 −80 dBFS fIN = 155 MHz −89 −85 −75 −77 dBFS fIN = 305 MHz −82 −82 −78 dBFS fIN = 450 MHz −82 −83 −77 dBFS fIN = 765 MHz −77 −75 −72 dBFS fIN = 985 MHz −82 −79 −76 dBFS Rev. 0 | Page 5 of 101 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Dither Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C, AND FD_D) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO AND MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS OVERVIEW HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE SETTING UP THE AD9694 DIGITAL INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) LATENCY END-TO-END TOTAL LATENCY MULTICHIP SYNCHRONIZATION SYSREF± SET UP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels ADC Pair Addressing Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE SUMMARY MEMORY MAP REGISTER TABLE—DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) OUTLINE DIMENSIONS ORDERING GUIDE