Datasheet AD9689 (Analog Devices) - 7

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AD9689 Data Sheet AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, sampling rate = 2.56 GHz, clock divider = 2, 1.7 V p-p ful -scale differential input, input amplitude (AIN) = −2.0 dBFS, default SPI settings, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).
Table 2. Parameter2 Min Typ Max Unit
NOISE DENSITY3 Full Scale = 1.7 V p-p −152 dBFS/Hz Full Scale = 2.0 V p-p −154 dBFS/Hz CODE ERROR RATE (CER) AVDD1 = 0.975 V 10−9 Errors AVDD1 = 1.0 V 10−10 Errors SIGNAL-TO-NOISE RATIO (SNR) fIN = 155 MHz 61.3 dBFS fIN = 155 MHz (Full Scale = 2.0 V p-p) 62.5 dBFS fIN = 750 MHz 61.0 dBFS fIN = 900 MHz 60.9 dBFS fIN = 1800 MHz 56.0 59.7 dBFS fIN = 2100 MHz 59.3 dBFS fIN = 3300 MHz 58.0 dBFS fIN = 4350 MHz (Full Scale = 1.1 V p-p) 54.0 dBFS fIN = 5530 MHz (Full Scale = 1.1 V p-p) 53.0 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 155 MHz 61.2 dBFS fIN = 155 MHz (Full Scale = 2.0 V p-p) 62.4 dBFS fIN = 750 MHz 60.7 dBFS fIN = 900 MHz 60.5 dBFS fIN = 1800 MHz 52.4 59.4 dBFS fIN = 2100 MHz 59.1 dBFS fIN = 3300 MHz 56.6 dBFS fIN = 4350 MHz (Full Scale = 1.1 V p-p) 51.0 dBFS fIN = 5530 MHz (Full Scale = 1.1 V p-p) 49.5 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 155 MHz 9.9 Bits fIN = 155 MHz (Full Scale = 2.0 V p-p) 10.1 Bits fIN = 750 MHz 9.8 Bits fIN = 900 MHz 9.8 Bits fIN = 1800 MHz 8.4 9.6 Bits fIN = 2100 MHz 9.5 Bits fIN = 3300 MHz 9.1 Bits fIN = 4350 MHz (Full Scale = 1.1 V p-p) 8.2 Bits fIN = 5530 MHz (Full Scale = 1.1 V p-p) 7.9 Bits SPURIOUS FREE DYNAMIC RANGE (SFDR), 2nd OR 3rd HARMONIC fIN = 155 MHz 78 dBFS fIN = 155 MHz (Full Scale = 2.0 V p-p) 78 dBFS fIN = 750 MHz 73 dBFS fIN = 900 MHz 74 dBFS fIN = 1800 MHz 58 73 dBFS fIN = 2100 MHz 73 dBFS fIN = 3300 MHz 64 dBFS fIN = 4350 MHz (Full Scale = 1.1 V p-p) 60 dBFS fIN = 5530 MHz (Full Scale = 1.1 V p-p) 59 dBFS Rev. 0 | Page 6 of 128 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Dither Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN AND STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FIR FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC Frequency Translation Stage (Optional) DDC Filtering Stage DDC Gain Stage (Optional) DDC Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS DDC POWER CONSUMPTION SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) fS × 4 MODE SETTING UP THE AD9689 DIGITAL INTERFACE Example 1—Full Bandwidth Mode Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF INPUT SYSREF Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER DETAILS Analog Devices SPI Registers Clock/SYSREF/Chip Power-Down Pin Control Registers Chip Operating Mode Control Registers Fast Detect and Signal Monitor Control Registers DDC Function Registers (See the Digital Downconverter (DDC) Section) Digital Outputs and Test Modes Programmable Filter (PFILT) Control and Coefficients Registers VREF/Analog Input Control Registers APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8) OUTLINE DIMENSIONS ORDERING GUIDE