Datasheet LT3761A (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 60VIN LED Controller with Internal PWM Generator |
| Páginas / Página | 30 / 9 — pin FuncTions OPENLED (Pin 9):. EN/UVLO (Pin 12):. DIM/SS (Pin 10):. … |
| Formato / tamaño de archivo | PDF / 660 Kb |
| Idioma del documento | Inglés |
pin FuncTions OPENLED (Pin 9):. EN/UVLO (Pin 12):. DIM/SS (Pin 10):. INTVCC (Pin 13):. IN (Pin 14):. SENSE (Pin 15):
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LT3761A
pin FuncTions OPENLED (Pin 9):
An open-drain pull-down on this pin
EN/UVLO (Pin 12):
Enable and Undervoltage Detect Pin. asserts if the FB input is greater than the FB regulation An accurate 1.22V falling threshold with externally pro- voltage (VFB) minus 50mV (typical) AND the difference grammable hysteresis causes the switching regulator to between current sense inputs ISP and ISN is less than shut down when power is insufficient to maintain output 25mV. To function, the pin requires an external pull-up regulation. Above the 1.24V (typical) rising enable threshold resistor, usually to INTVCC. When the PWM input is low (but below 2.5V), EN/UVLO input bias current is sub-μA. and the DC/DC converter is idle, the OPENLED condition Below the 1.22V (typical) falling threshold, an accurate is latched to the last valid state when the PWM input was 2.3μA (typical) pull-down current is enabled so the user high. When PWM input goes high again, the OPENLED can define the rising hysteresis with the external resistor pin will be updated. This pin may be used to report transi- selection. An undervoltage condition causes the GATE tion from constant current regulation to constant voltage and PWMOUT pins to transition low and resets soft-start. regulation modes, for instance in a charger or current Tie to 0.4V, or less, to disable the device and reduce VIN limited voltage supply. quiescent current below 1μA.
DIM/SS (Pin 10):
Soft-Start and PWMOUT Dimming Signal
INTVCC (Pin 13):
Current limited, low dropout linear regula- Generator Programming Pin. This pin modulates switching tor regulates to 7.85V (typical) from VIN. Supplies internal regulator frequency and compensation pin voltage (VC) loads, GATE and PWMOUT drivers. Must be bypassed with clamp when it is below 1V. The soft-start interval is set a 1µF ceramic capacitor placed close to the pin and to the with an external capacitor and the DIM/SS pin charging exposed pad GND of the IC. current. The pin has an internal 14μA (typical) pull-up
V
current source. The soft-start pin is reset to GND by an
IN (Pin 14):
Power Supply for Internal Loads and INTVCC Regulator. Must be locally bypassed with a 0.22µF (or undervoltage condition (detected at the EN/UVLO pin), larger) low ESR capacitor placed close to the pin. INTVCC undervoltage, overcurrent event sensed at ISP/ ISN, or thermal limit. After initial start-up with EN/UVLO,
SENSE (Pin 15):
The Current Sense Input for the Switch DIM/SS is forced low until the first PWM rising edge. When Control Loop. Kelvin connect the SENSE pin to the positive DIM/SS reaches the steady-state voltage (~1.17V), the terminal of the switch current sense resistor in the source charging current (sum of internal and external currents) is of the external power NFET. The negative terminal of the sensed and used to set the PWM pin charging and discharge switch current sense resistor should be Kelvin connected currents and threshold hysteresis. In this manner, the SS to the exposed pad (GND) of the LT3761A. charging current sets the duty cycle of the PWMOUT signal
GATE (Pin 16):
N-channel FET Gate Driver Output. Switches generator associated with the PWM pin. This pin should between INTV always have a capacitor to GND, minimum 560pF value, CC and GND. Driven to GND during shutdown, fault or idle states. when used with the PWMOUT signal generator function. Place the PWM pin capacitor close to the IC.
GND (Exposed Pad Pin 17):
Ground. This pin also serves as current sense input for the control loop, sensing the
RT (Pin 11):
Switching Frequency Adjustment Pin. Set the negative terminal of the current sense resistor. Solder the frequency using a resistor to GND (for resistor values, see exposed pad directly to the ground plane. the Typical Performance curve or Table 2). Do not leave the RT pin open. Place the resistor close to the IC. 3761af For more information www.linear.com/LT3761A 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
pin FuncTions OPENLED (Pin 9):
An open-drain pull-down on this pin
EN/UVLO (Pin 12):
Enable and Undervoltage Detect Pin. asserts if the FB input is greater than the FB regulation An accurate 1.22V falling threshold with externally pro- voltage (VFB) minus 50mV (typical) AND the difference grammable hysteresis causes the switching regulator to between current sense inputs ISP and ISN is less than shut down when power is insufficient to maintain output 25mV. To function, the pin requires an external pull-up regulation. Above the 1.24V (typical) rising enable threshold resistor, usually to INTVCC. When the PWM input is low (but below 2.5V), EN/UVLO input bias current is sub-μA. and the DC/DC converter is idle, the OPENLED condition Below the 1.22V (typical) falling threshold, an accurate is latched to the last valid state when the PWM input was 2.3μA (typical) pull-down current is enabled so the user high. When PWM input goes high again, the OPENLED can define the rising hysteresis with the external resistor pin will be updated. This pin may be used to report transi- selection. An undervoltage condition causes the GATE tion from constant current regulation to constant voltage and PWMOUT pins to transition low and resets soft-start. regulation modes, for instance in a charger or current Tie to 0.4V, or less, to disable the device and reduce VIN limited voltage supply. quiescent current below 1μA.
DIM/SS (Pin 10):
Soft-Start and PWMOUT Dimming Signal
INTVCC (Pin 13):
Current limited, low dropout linear regula- Generator Programming Pin. This pin modulates switching tor regulates to 7.85V (typical) from VIN. Supplies internal regulator frequency and compensation pin voltage (VC) loads, GATE and PWMOUT drivers. Must be bypassed with clamp when it is below 1V. The soft-start interval is set a 1µF ceramic capacitor placed close to the pin and to the with an external capacitor and the DIM/SS pin charging exposed pad GND of the IC. current. The pin has an internal 14μA (typical) pull-up
V
current source. The soft-start pin is reset to GND by an
IN (Pin 14):
Power Supply for Internal Loads and INTVCC Regulator. Must be locally bypassed with a 0.22µF (or undervoltage condition (detected at the EN/UVLO pin), larger) low ESR capacitor placed close to the pin. INTVCC undervoltage, overcurrent event sensed at ISP/ ISN, or thermal limit. After initial start-up with EN/UVLO,
SENSE (Pin 15):
The Current Sense Input for the Switch DIM/SS is forced low until the first PWM rising edge. When Control Loop. Kelvin connect the SENSE pin to the positive DIM/SS reaches the steady-state voltage (~1.17V), the terminal of the switch current sense resistor in the source charging current (sum of internal and external currents) is of the external power NFET. The negative terminal of the sensed and used to set the PWM pin charging and discharge switch current sense resistor should be Kelvin connected currents and threshold hysteresis. In this manner, the SS to the exposed pad (GND) of the LT3761A. charging current sets the duty cycle of the PWMOUT signal
GATE (Pin 16):
N-channel FET Gate Driver Output. Switches generator associated with the PWM pin. This pin should between INTV always have a capacitor to GND, minimum 560pF value, CC and GND. Driven to GND during shutdown, fault or idle states. when used with the PWMOUT signal generator function. Place the PWM pin capacitor close to the IC.
GND (Exposed Pad Pin 17):
Ground. This pin also serves as current sense input for the control loop, sensing the
RT (Pin 11):
Switching Frequency Adjustment Pin. Set the negative terminal of the current sense resistor. Solder the frequency using a resistor to GND (for resistor values, see exposed pad directly to the ground plane. the Typical Performance curve or Table 2). Do not leave the RT pin open. Place the resistor close to the IC. 3761af For more information www.linear.com/LT3761A 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts