Datasheet LT3475, LT3475-1 (Analog Devices) - 6

FabricanteAnalog Devices
DescripciónDual Step-Down 1.5A LED Driver
Páginas / Página20 / 6 — PI FU CTIO S. RT (Pin 14):. VC1, VC2 (Pins 18, 13):. SHDN (Pin 16):. …
Formato / tamaño de archivoPDF / 249 Kb
Idioma del documentoInglés

PI FU CTIO S. RT (Pin 14):. VC1, VC2 (Pins 18, 13):. SHDN (Pin 16):. VADJ1, VADJ2 (Pins 19, 12):. REF (Pin 17):

PI FU CTIO S RT (Pin 14): VC1, VC2 (Pins 18, 13): SHDN (Pin 16): VADJ1, VADJ2 (Pins 19, 12): REF (Pin 17):

Línea de modelo para esta hoja de datos

Versión de texto del documento

LT3475/LT3475-1
U U U PI FU CTIO S RT (Pin 14):
The RT pin is used to set the internal
VC1, VC2 (Pins 18, 13):
The VC pin is the output of the oscillator frequency. Tie a 24.3k resistor from RT to GND internal error amp. The voltage on this pin controls the for a 600kHz switching frequency. peak switch current. Use this pin to compensate the control loop.
SHDN (Pin 16):
The SHDN pin is used to shut down the switching regulator and the internal bias circuits. The
VADJ1, VADJ2 (Pins 19, 12):
The VADJ pin is the input to 2.6V switching threshold can function as an accurate the internal voltage-to-current amplifi er. Connect the VADJ undervoltage lockout. Pull below 0.3V to shut down the pin to the REF pin for a 1.5A output current. For lower LT3475/LT3475-1. Pull above 2.6V to enable the LT3475/ output currents, program the VADJ pin using the following LT3475-1. Tie to VIN if the SHDN function is unused. formula: ILED = 1.5A • VADJ/1.25V.
REF (Pin 17):
The REF pin is the buffered output of the
PWM1, PWM2 (Pins 20, 11):
The PWM pin controls the internal reference. Either tie the REF pin to the VADJ pin connection of the VC pin to the internal circuitry. When for a 1.5A output current, or use a resistor divider to the PWM pin is low, the VC pin is disconnected from the generate a lower voltage at the VADJ pin. Leave this pin internal circuitry and draws minimal current. If the PWM unconnected if unused. feature is unused, leave this pin unconnected.
BLOCK DIAGRAM
VIN CIN RT V SHDN R V IN T IN INT REG MASTER AND OSC UVLO D1 D2 BOOST1 BOOST2 C1 SLOPE COMP SLOPE COMP C2 C1 ∑ ∑ C2 Q R R Q MOSC 1 MOSC 2 Q S S Q Q1 SLAVE SLAVE Q2 SW1 L1 OSC OSC SW2 L2 DRIVER DRIVER D3 FREQUENCY FREQUENCY D4 FOLDBACK FOLDBACK OUT1 OUT2 – – COUT1 C 0.067Ω 100Ω 100Ω 0.067Ω OUT2 LED1 + + LED2 2V 2V gm1 gm2 DLED1 DLED 2 1.25V PWM 1 PWM2 Q3 Q4 VC1 VC2 1.25k 1.25k CC1 CC2 VADJ1 REF VADJ2 EXPOSED GND PAD 3475 BD 3475fb 6