Datasheet LTC3588-2 (Analog Devices) - 9

LTC3588-2
OPERATION
When the sleep comparator signals that the output has regulation voltage. Several sleep cycles may occur during reached the sleep threshold the buck converter may be this time. Additionally, if PGOOD is high and VIN falls below in the middle of a cycle with current still flowing through the UVLO falling threshold, PGOOD will remain high until the inductor. Normally both synchronous switches would VOUT falls to 92% of the desired regulation point. This turn off and the current in the inductor would freewheel allows output energy to be used even if the input is lost. to zero through the NMOS body diode. The LTC3588-2 Figure 2 shows the behavior for VOUT = 5V and a 10µA keeps the NMOS switch on during this time to prevent the load. At t = 2s VIN becomes high impedance and is dis- conduction loss that would occur in the diode if the NMOS charged by the quiescent current of the LTC3588-2 and were off. If the PMOS is on when the sleep comparator through servicing VOUT which is discharged by its own trips the NMOS will turn on immediately in order to ramp leakage current. VIN crosses UVLO falling but PGOOD down the current. If the NMOS is on it will be kept on until remains high until VOUT decreases to 92% of the desired the current reaches zero. regulation point. The PGOOD pin is designed to drive a Though the quiescent current when the buck is switching microprocessor or other chip I/O and is not intended to is much greater than the sleep quiescent current, it is still drive higher current loads such as an LED. a small percentage of the average inductor current which The D0/D1 inputs can be switched while in regulation as results in high efficiency over most load conditions. The shown in Figure 3. If VOUT is programmed to a voltage with buck operates only when sufficient energy has been ac- a PGOOD falling threshold above the old VOUT, PGOOD will cumulated in the input capacitor and the length of time the 20 converter needs to transfer energy to the output is much 18 less than the time it takes to accumulate energy. Thus, the VIN 16 buck operating quiescent current is averaged over a long VIN = UVLO FALLING 14 period of time so that the total average quiescent current 12 C is low. This feature accommodates sources that harvest IN = 10µF, 10 COUT = 47µF, TAGE (V) small amounts of ambient energy. ILOAD = 10µA VOL 8 Four selectable voltages are available by tying the output 6 V select bits, D0 and D1, to GND or V 4 OUT IN2. Table 1 shows the four D0/D1 codes and their corresponding output voltages. 2 PGOOD 0 0 2 4 6 8 10 12
Table 1. Output Voltage Selection
TIME (sec) 35882 F02
D1 D0 VOUT VOUT QUIESCENT CURRENT (IVOUT) Figure 2. PGOOD Operation During Transition to UVLO
0 0 3.45V 86nA 0 1 4.1V 101nA 6 COUT = 100µF, ILOAD = 100mA 1 0 4.5V 111nA 5 D1=D0=0 D1=D0=1 D1=D0=0 1 1 5.0V 125nA The internal feedback network draws a small amount of 4 VOUT current from VOUT as listed in Table 1. TAGE (V) 3 VOL
Power Good Comparator
V OUT 2 A power good comparator produces a logic high referenced PGOOD = LOGIC 1 1 to VOUT on the PGOOD pin the first time the converter reaches the sleep threshold of the programmed V 0 OUT, 0 2 4 6 8 10 12 14 16 18 20 signaling that the output is in regulation. The PGOOD pin TIME (ms) 35882 F03 will remain high until VOUT falls to 92% of the desired
Figure 3. PGOOD Operation During D0/D1 Transition
35882fc For more information www.linear.com/LTC3588-2 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Revision History Typical Application Related Parts