Datasheet ATmega164A - Complete (Atmel)

8-bit AVR Microcontrollers ATmega164A DATASHEET COMPLETE Introduction
The Atmel® ATmega164A is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
Feature
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family • Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – 16KBytes of In-System Self-Programmable Flash Program Memory – 512Bytes EEPROM – 1KBytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 Years at 85°C/100 Years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security • Atmel QTouch® Library Support – Capacitive Touch Buttons, Sliders and Wheels – QTouch and QMatrix acquisition – Up to 64 Sense Channels Atmel-42712C-ATmega164A_Datasheet_Complete-10/2016 Document Outline Introduction Feature Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. Pin Configurations 5.1. Pinout 5.1.1. PDIP 5.1.2. TQFN and QFN 5.1.3. DRQFN 5.1.4. VFBGA 5.2. Pin Descriptions 5.2.1. VCC 5.2.2. GND 5.2.3. Port A (PA[7:0]) 5.2.4. Port B (PB[7:0]) 5.2.5. Port C (PC[7:0]) 5.2.6. Port D (PD[7:0]) 5.2.7. RESET 5.2.8. XTAL1 5.2.9. XTAL2 5.2.10. AVCC 5.2.11. AREF 6. I/O Multiplexing 7. General Information 7.1. Resources 7.2. Data Retention 7.3. About Code Examples 7.4. Capacitive Touch Sensing 7.4.1. QTouch Library 8. AVR CPU Core 8.1. Overview 8.2. ALU – Arithmetic Logic Unit 8.3. Status Register 8.3.1. Status Register 8.4. General Purpose Register File 8.4.1. The X-register, Y-register, and Z-register 8.5. Stack Pointer 8.5.1. Stack Pointer Register Low and High byte 8.6. Accessing 16-bit Registers 8.7. Instruction Execution Timing 8.8. Reset and Interrupt Handling 8.8.1. Interrupt Response Time 9. AVR Memories 9.1. Overview 9.2. In-System Reprogrammable Flash Program Memory 9.3. SRAM Data Memory 9.3.1. Data Memory Access Times 9.4. EEPROM Data Memory 9.4.1. EEPROM Read/Write Access 9.4.2. Preventing EEPROM Corruption 9.5. I/O Memory 9.5.1. General Purpose I/O Registers 9.6. Register Description 9.6.1. Accessing 16-bit Registers 9.6.2. EEPROM Address Register Low and High Byte 9.6.3. EEPROM Data Register 9.6.4. EEPROM Control Register 9.6.5. GPIOR2 – General Purpose I/O Register 2 9.6.6. GPIOR1 – General Purpose I/O Register 1 9.6.7. GPIOR0 – General Purpose I/O Register 0 10. System Clock and Clock Options 10.1. Clock Systems and Their Distribution 10.1.1. CPU Clock – clkCPU 10.1.2. I/O Clock – clkI/O 10.1.3. Flash Clock – clkFLASH 10.1.4. Asynchronous Timer Clock – clkASY 10.1.5. ADC Clock – clkADC 10.2. Clock Sources 10.2.1. Default Clock Source 10.2.2. Clock Startup Sequence 10.2.3. Clock Source Connections 10.3. Low Power Crystal Oscillator 10.4. Full Swing Crystal Oscillator 10.5. Low Frequency Crystal Oscillator 10.6. Calibrated Internal RC Oscillator 10.7. 128kHz Internal Oscillator 10.8. External Clock 10.9. Timer/Counter Oscillator 10.10. Clock Output Buffer 10.11. System Clock Prescaler 10.12. Register Description 10.12.1. Oscillator Calibration Register 10.12.2. Clock Prescaler Register 11. PM - Power Management and Sleep Modes 11.1. Overview 11.2. Sleep Modes 11.3. BOD Disable 11.4. Idle Mode 11.5. ADC Noise Reduction Mode 11.6. Power-Down Mode 11.7. Power-Save Mode 11.8. Standby Mode 11.9. Extended Standby Mode 11.10. Power Reduction Register 11.11. Minimizing Power Consumption 11.11.1. Analog to Digital Converter 11.11.2. Analog Comparator 11.11.3. Brown-Out Detector 11.11.4. Internal Voltage Reference 11.11.5. Watchdog Timer 11.11.6. Port Pins 11.11.7. On-chip Debug System 11.12. Register Description 11.12.1. Sleep Mode Control Register 11.12.2. MCU Control Register 11.12.3. Power Reduction Register 0 12. SCRST - System Control and Reset 12.1. Resetting the AVR 12.2. Reset Sources 12.3. Power-on Reset 12.4. External Reset 12.5. Brown-out Detection 12.6. Watchdog System Reset 12.7. Internal Voltage Reference 12.7.1. Voltage Reference Enable Signals and Start-up Time 12.8. Watchdog Timer 12.8.1. Features 12.8.2. Overview 12.9. Register Description 12.9.1. MCU Status Register 12.9.2. WDTCSR – Watchdog Timer Control Register 13. Interrupts 13.1. Overview 13.2. Interrupt Vectors in ATmega164A 13.3. Register Description 13.3.1. Moving Interrupts Between Application and Boot Space 13.3.2. MCU Control Register 14. External Interrupts 14.1. EXINT - External Interrupts 14.1.1. Pin Change Interrupt Timing 14.1.2. Register Description 14.1.2.1. External Interrupt Control Register A 14.1.2.2. External Interrupt Mask Register 14.1.2.3. External Interrupt Flag Register 14.1.2.4. Pin Change Interrupt Control Register 14.1.2.5. Pin Change Interrupt Flag Register 14.1.2.6. Pin Change Mask Register 0 14.1.2.7. Pin Change Mask Register 1 14.1.2.8. Pin Change Mask Register 2 14.1.2.9. Pin Change Mask Register 3 15. I/O-Ports 15.1. Overview 15.2. Ports as General Digital I/O 15.2.1. Configuring the Pin 15.2.2. Toggling the Pin 15.2.3. Switching Between Input and Output 15.2.4. Reading the Pin Value 15.2.5. Digital Input Enable and Sleep Modes 15.2.6. Unconnected Pins 15.3. Alternate Port Functions 15.3.1. Alternate Functions of Port A 15.3.2. Alternate Functions of Port B 15.3.3. Alternate Functions of Port C 15.3.4. Alternate Functions of Port D 15.4. Register Description 15.4.1. MCU Control Register 15.4.2. Port A Data Register 15.4.3. Port A Data Direction Register 15.4.4. Port A Input Pins Address 15.4.5. Port B Data Register 15.4.6. Port B Data Direction Register 15.4.7. Port B Input Pins Address 15.4.8. Port C Data Register 15.4.9. Port C Data Direction Register 15.4.10. Port C Input Pins Address 15.4.11. Port D Data Register 15.4.12. Port D Data Direction Register 15.4.13. Port D Input Pins Address 16. TC0 - 8-bit Timer/Counter0 with PWM 16.1. Features 16.2. Overview 16.2.1. Definitions 16.2.2. Registers 16.3. Timer/Counter Clock Sources 16.4. Counter Unit 16.5. Output Compare Unit 16.5.1. Force Output Compare 16.5.2. Compare Match Blocking by TCNT0 Write 16.5.3. Using the Output Compare Unit 16.6. Compare Match Output Unit 16.6.1. Compare Output Mode and Waveform Generation 16.7. Modes of Operation 16.7.1. Normal Mode 16.7.2. Clear Timer on Compare Match (CTC) Mode 16.7.3. Fast PWM Mode 16.7.4. Phase Correct PWM Mode 16.8. Timer/Counter Timing Diagrams 16.9. Register Description 16.9.1. TC0 Control Register A 16.9.2. TC0 Control Register B 16.9.3. TC0 Interrupt Mask Register 16.9.4. General Timer/Counter Control Register 16.9.5. TC0 Counter Value Register 16.9.6. TC0 Output Compare Register A 16.9.7. TC0 Output Compare Register B 16.9.8. TC0 Interrupt Flag Register 17. TC1 - 16-bit Timer/Counter1 with PWM 17.1. Overview 17.2. Features 17.3. Block Diagram 17.4. Definitions 17.5. Registers 17.6. Accessing 16-bit Timer/Counter Registers 17.6.1. Reusing the Temporary High Byte Register 17.7. Timer/Counter Clock Sources 17.8. Counter Unit 17.9. Input Capture Unit 17.9.1. Input Capture Trigger Source 17.9.2. Noise Canceler 17.9.3. Using the Input Capture Unit 17.10. Output Compare Units 17.10.1. Force Output Compare 17.10.2. Compare Match Blocking by TCNT1 Write 17.10.3. Using the Output Compare Unit 17.11. Compare Match Output Unit 17.11.1. Compare Output Mode and Waveform Generation 17.12. Modes of Operation 17.12.1. Normal Mode 17.12.2. Clear Timer on Compare Match (CTC) Mode 17.12.3. Fast PWM Mode 17.12.4. Phase Correct PWM Mode 17.12.5. Phase and Frequency Correct PWM Mode 17.13. Timer/Counter Timing Diagrams 17.14. Register Description 17.14.1. TC1 Control Register A 17.14.2. TC1 Control Register B 17.14.3. TC1 Control Register C 17.14.4. TC1 Counter Value Low and High byte 17.14.5. Input Capture Register 1 Low and High byte 17.14.6. Output Compare Register 1 A Low and High byte 17.14.7. Output Compare Register 1 B Low and High byte 17.14.8. Timer/Counter 1 Interrupt Mask Register 17.14.9. TC1 Interrupt Flag Register 18. Timer/Counter 0, 1 Prescalers 18.1. Internal Clock Source 18.2. Prescaler Reset 18.3. External Clock Source 18.4. Register Description 18.4.1. General Timer/Counter Control Register 19. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 19.1. Features 19.2. Overview 19.2.1. Definitions 19.2.2. Registers 19.3. Timer/Counter Clock Sources 19.4. Counter Unit 19.5. Output Compare Unit 19.5.1. Force Output Compare 19.5.2. Compare Match Blocking by TCNT2 Write 19.5.3. Using the Output Compare Unit 19.6. Compare Match Output Unit 19.6.1. Compare Output Mode and Waveform Generation 19.7. Modes of Operation 19.7.1. Normal Mode 19.7.2. Clear Timer on Compare Match (CTC) Mode 19.7.3. Fast PWM Mode 19.7.4. Phase Correct PWM Mode 19.8. Timer/Counter Timing Diagrams 19.9. Asynchronous Operation of Timer/Counter2 19.10. Timer/Counter Prescaler 19.11. Register Description 19.11.1. TC2 Control Register A 19.11.2. TC2 Control Register B 19.11.3. TC2 Counter Value Register 19.11.4. TC2 Output Compare Register A 19.11.5. TC2 Output Compare Register B 19.11.6. TC2 Interrupt Mask Register 19.11.7. TC2 Interrupt Flag Register 19.11.8. Asynchronous Status Register 19.11.9. General Timer/Counter Control Register 20. SPI – Serial Peripheral Interface 20.1. Features 20.2. Overview 20.3. SS Pin Functionality 20.3.1. Slave Mode 20.3.2. Master Mode 20.4. Data Modes 20.5. Register Description 20.5.1. SPI Control Register 0 20.5.2. SPI Status Register 0 20.5.3. SPI Data Register 0 21. USART - Universal Synchronous Asynchronous Receiver Transceiver 21.1. Features 21.2. Overview 21.3. Block Diagram 21.4. Clock Generation 21.4.1. Internal Clock Generation – The Baud Rate Generator 21.4.2. Double Speed Operation (U2X) 21.4.3. External Clock 21.4.4. Synchronous Clock Operation 21.5. Frame Formats 21.5.1. Parity Bit Calculation 21.6. USART Initialization 21.7. Data Transmission – The USART Transmitter 21.7.1. Sending Frames with 5 to 8 Data Bits 21.7.2. Sending Frames with 9 Data Bit 21.7.3. Transmitter Flags and Interrupts 21.7.4. Parity Generator 21.7.5. Disabling the Transmitter 21.8. Data Reception – The USART Receiver 21.8.1. Receiving Frames with 5 to 8 Data Bits 21.8.2. Receiving Frames with 9 Data Bits 21.8.3. Receive Compete Flag and Interrupt 21.8.4. Receiver Error Flags 21.8.5. Parity Checker 21.8.6. Disabling the Receiver 21.8.7. Flushing the Receive Buffer 21.9. Asynchronous Data Reception 21.9.1. Asynchronous Clock Recovery 21.9.2. Asynchronous Data Recovery 21.9.3. Asynchronous Operational Range 21.10. Multi-Processor Communication Mode 21.10.1. Using MPCMn 21.11. Examples of Baud Rate Setting 21.12. Register Description 21.12.1. USART I/O Data Register n 21.12.2. USART Control and Status Register n A 21.12.3. USART Control and Status Register n B 21.12.4. USART Control and Status Register n C 21.12.5. USART Baud Rate n Register Low and High byte 22. USARTSPI - USART in SPI Mode 22.1. Features 22.2. Overview 22.3. Clock Generation 22.4. SPI Data Modes and Timing 22.5. Frame Formats 22.5.1. USART MSPIM Initialization 22.6. Data Transfer 22.6.1. Transmitter and Receiver Flags and Interrupts 22.6.2. Disabling the Transmitter or Receiver 22.7. AVR USART MSPIM vs. AVR SPI 22.8. Register Description 23. TWI - 2-wire Serial Interface 23.1. Features 23.2. Two-Wire Serial Interface Bus Definition 23.2.1. TWI Terminology 23.2.2. Electrical Interconnection 23.3. Data Transfer and Frame Format 23.3.1. Transferring Bits 23.3.2. START and STOP Conditions 23.3.3. Address Packet Format 23.3.4. Data Packet Format 23.3.5. Combining Address and Data Packets into a Transmission 23.4. Multi-master Bus Systems, Arbitration, and Synchronization 23.5. Overview of the TWI Module 23.5.1. SCL and SDA Pins 23.5.2. Bit Rate Generator Unit 23.5.3. Bus Interface Unit 23.5.4. Address Match Unit 23.5.5. Control Unit 23.6. Using the TWI 23.7. Transmission Modes 23.7.1. Master Transmitter Mode 23.7.2. Master Receiver Mode 23.7.3. Slave Transmitter Mode 23.7.4. Slave Receiver Mode 23.7.5. Miscellaneous States 23.7.6. Combining Several TWI Modes 23.8. Multi-master Systems and Arbitration 23.9. Register Description 23.9.1. TWI Bit Rate Register 23.9.2. TWI Status Register 23.9.3. TWI (Slave) Address Register 23.9.4. TWI Data Register 23.9.5. TWI Control Register 23.9.6. TWI (Slave) Address Mask Register 24. AC - Analog Comparator 24.1. Overview 24.2. Analog Comparator Multiplexed Input 24.3. Register Description 24.3.1. Analog Comparator Control and Status Register 24.3.2. Digital Input Disable Register 1 25. ADC - Analog to Digital Converter 25.1. Features 25.2. Overview 25.3. Starting a Conversion 25.4. Prescaling and Conversion Timing 25.4.1. Differential Gain Channels 25.5. Changing Channel or Reference Selection 25.5.1. ADC Input Channels 25.5.2. ADC Voltage Reference 25.6. ADC Noise Canceler 25.6.1. Analog Input Circuitry 25.6.2. Analog Noise Canceling Techniques 25.6.3. Offset Compensation Schemes 25.6.4. ADC Accuracy Definitions 25.7. ADC Conversion Result 25.8. Register Description 25.8.1. ADC Multiplexer Selection Register 25.8.2. ADC Control and Status Register A 25.8.3. ADC Data Register Low and High Byte (ADLAR=0) 25.8.4. ADC Data Register Low and High Byte (ADLAR=1) 25.8.5. ADC Control and Status Register B 25.8.6. Digital Input Disable Register 0 26. JTAG Interface and On-chip Debug System 26.1. Features 26.2. Overview 26.3. TAP – Test Access Port 26.4. TAP Controller 26.5. Using the Boundary-scan Chain 26.6. Using the On-chip Debug System 26.7. On-chip Debug Specific JTAG Instructions 26.8. Using the JTAG Programming Capabilities 26.9. Bibliography 26.10. IEEE 1149.1 (JTAG) Boundary-scan 26.10.1. Features 26.10.2. System Overview 26.11. Data Registers 26.11.1. Bypass Register 26.11.2. Device Identification Register 26.11.2.1. Version 26.11.2.2. Part Number 26.11.2.3. Manufacturer ID 26.11.3. Reset Register 26.11.4. Boundary-scan Chain 26.12. Boundry-scan Specific JTAG Instructions 26.12.1. EXTEST; 0x0 26.12.2. IDCODE; 0x1 26.12.3. SAMPLE_PRELOAD; 0x2 26.12.4. AVR_RESET; 0xC 26.12.5. BYPASS; 0xF 26.13. Boundary-scan Chain 26.13.1. Scanning the Digital Port Pins 26.13.2. Scanning the RESET Pin 26.14. ATmega164A Boundary-scan Order 26.15. Boundary-scan Description Language Files 26.16. Register Description 26.16.1. OCDR – On-chip Debug Register 26.16.2. MCU Control Register 26.16.3. MCU Status Register 27. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 27.1. Features 27.2. Overview 27.3. Application and Boot Loader Flash Sections 27.3.1. Application Section 27.3.2. BLS – Boot Loader Section 27.4. Read-While-Write and No Read-While-Write Flash Sections 27.4.1. RWW – Read-While-Write Section 27.4.2. NRWW – No Read-While-Write Section 27.5. Entering the Boot Loader Program 27.6. Boot Loader Lock Bits 27.7. Addressing the Flash During Self-Programming 27.8. Self-Programming the Flash 27.8.1. Performing Page Erase by SPM 27.8.2. Filling the Temporary Buffer (Page Loading) 27.8.3. Performing a Page Write 27.8.4. Using the SPM Interrupt 27.8.5. Consideration While Updating Boot Loader Section (BLS) 27.8.6. Prevent Reading the RWW Section During Self-Programming 27.8.7. Setting the Boot Loader Lock Bits by SPM 27.8.8. EEPROM Write Prevents Writing to SPMCSR 27.8.9. Reading the Fuse and Lock Bits from Software 27.8.10. Reading the Signature Row from Software 27.8.11. Preventing Flash Corruption 27.8.12. Programming Time for Flash when Using SPM 27.8.13. Simple Assembly Code Example for a Boot Loader 27.8.14. ATmega164A Boot Loader Parameters 27.9. Register Description 27.9.1. SPMCSR – Store Program Memory Control and Status Register 28. MEMPROG- Memory Programming 28.1. Program And Data Memory Lock Bits 28.2. Fuse Bits 28.2.1. Latching of Fuses 28.3. Signature Bytes 28.4. Calibration Byte 28.5. Serial Number 28.6. Page Size 28.7. Parallel Programming Parameters, Pin Mapping, and Commands 28.7.1. Signal Names 28.8. Parallel Programming 28.8.1. Enter Programming Mode 28.8.2. Considerations for Efficient Programming 28.8.3. Chip Erase 28.8.4. Programming the Flash 28.8.5. Programming the EEPROM 28.8.6. Reading the Flash 28.8.7. Reading the EEPROM 28.8.8. Programming the Fuse Low Bits 28.8.9. Programming the Fuse High Bits 28.8.10. Programming the Extended Fuse Bits 28.8.11. Programming the Lock Bits 28.8.12. Reading the Fuse and Lock Bits 28.8.13. Reading the Signature Bytes 28.8.14. Reading the Calibration Byte 28.8.15. Parallel Programming Characteristics 28.9. Serial Downloading 28.9.1. Serial Programming Pin Mapping 28.9.2. Serial Programming Algorithm 28.9.3. Serial Programming Instruction Set 28.9.4. SPI Serial Programming Characteristics 28.10. Programming Via the JTAG Interface 28.10.1. Programming Specific JTAG Instructions 28.10.2. AVR_RESET (0xC) 28.10.3. PROG_ENABLE (0x4) 28.10.4. PROG_COMMANDS (0x5) 28.10.5. PROG_PAGELOAD (0x6) 28.10.6. PROG_PAGEREAD (0x7) 28.10.7. Data Registers 28.10.8. Reset Register 28.10.9. Programming Enable Register 28.10.10. Programming Command Register 28.10.11. Virtual Flash Page Load Register 28.10.12. Virtual Flash Page Read Register 28.10.13. Programming Algorithm 28.10.14. Entering Programming Mode 28.10.15. Leaving Programming Mode 28.10.16. Performing Chip Erase 28.10.17. Programming the Flash 28.10.18. Reading the Flash 28.10.19. Programming the EEPROM 28.10.20. Reading the EEPROM 28.10.21. Programming the Fuses 28.10.22. Programming the Lock Bits 28.10.23. Reading the Fuses and Lock Bits 28.10.24. Reading the Signature Bytes 28.10.25. Reading the Calibration Byte 29. Electrical Characteristics 29.1. Absolute Maximum Ratings 29.2. DC Characteristics 29.2.1. Power Consumption 29.3. Speed Grades 29.4. Clock Characteristics 29.4.1. Clock characteristics 29.4.2. External Clock Drive Waveforms 29.4.3. External Clock Drive 29.5. System and Reset Characteristics 29.6. External interrupts characteristics 29.7. SPI Timing Characteristics 29.8. Two-wire Serial Interface Characteristics 29.9. ADC characteristics 29.10. Parallel Programming Characteristics 30. Typical Characteristics 30.1. Active Supply Current 30.2. Idle Supply Current 30.3. Supply Current of I/O Modules 30.4. Power-down Supply Current 30.5. Power-save Supply Current 30.6. Standby Supply Current 30.7. Pin Pull-Up 30.8. Pin Driver Strength 30.9. Pin Threshold and Hysteresis 30.10. BOD Threshold 30.11. Internal Oscillator Speed 30.12. Current Consumption of Peripheral Units 30.13. Current Consumption in Reset and Reset Pulse Width 31. Register Summary 32. Instruction Set Summary 33. Packaging Information 33.1. 40-pin PDIP 33.2. 44-pin TQFP 33.3. 44-pin VQFN 33.4. 44-pin QFN 33.5. 49-pin VFBGA 34. Datasheet Revision History 34.1. Rev. C – 10/2016 34.2. Rev. B – 08/2016 34.3. Rev. A – 05/2016 35. Errata 35.1. Rev. E