Datasheet LTC3862 (Linear Technology) - 9
| Fabricante | Linear Technology |
| Descripción | Multi-Phase Current Mode Step-Up DC/DC Controller |
| Páginas / Página | 42 / 9 — pin FuncTions (SSOP/QFN/TSSOP). 3V8 (Pin 24/Pin 22/Pin 24):. INTVCC (Pin … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 1.0 Mb |
| Idioma del documento | Inglés |
pin FuncTions (SSOP/QFN/TSSOP). 3V8 (Pin 24/Pin 22/Pin 24):. INTVCC (Pin 19/Pin 17/Pin 19):. ITH (Pin 7/Pin 5/Pin 7):
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LTC3862
pin FuncTions (SSOP/QFN/TSSOP) 3V8 (Pin 24/Pin 22/Pin 24):
Output of the Internal 3.8V
INTVCC (Pin 19/Pin 17/Pin 19):
Output of the Internal 5V LDO from INTVCC. Supply pin for the low voltage analog Low Dropout Regulator (LDO). A low ESR 4.7µF (X5R or and digital circuits. A low ESR 1nF ceramic bypass capacitor better) ceramic bypass capacitor should be connected should be connected between 3V8 and SGND, as close between INTVCC and PGND, as close as possible to the IC. as possible to the IC.
ITH (Pin 7/Pin 5/Pin 7):
Error Amplifier Output. The current
BLANK (Pin 3/Pin 1/Pin 3):
Blanking Time. Floating this comparator trip threshold increases with the ITH control pin provides a nominal minimum on-time of 260ns. Con- voltage. The ITH pin is also used for compensating the necting this pin to 3V8 provides a minimum on-time of control loop of the converter. 340ns, while connecting it to SGND provides a minimum
PGND (Pin 17/Pin 15, Exposed Pad Pin 25/Pin 17,
on-time of 180ns.
Exposed Pad Pin 25):
Power Ground. Connect this pin
CLKOUT (Pin 10/Pin 8/Pin 10):
Digital Output Used for close to the sources of the power MOSFETs. PGND should Daisy-Chaining Multiple LTC3862 ICs in Multi-Phase also be connected to the negative terminals of VIN and Systems. The PHASEMODE pin voltage controls the INTVCC bypass capacitors. PGND is electrically isolated relationship between CH1 and CH2 as well as between from the SGND pin. The Exposed Pad of the FE and QFN CH1 and CLKOUT. packages is connected to PGND and must be soldered
D
to PCB ground for electrical contact and rated thermal
MAX (Pin 1/Pin 23/Pin 1):
Maximum Duty Cycle. This pin programs the maximum duty cycle. Floating this pin pro- performance. vides 84% duty cycle. Connecting this pin to 3V8 provides
PHASEMODE (Pin 4/Pin 2/Pin 4):
The PHASEMODE pin 75% duty cycle, while connecting it to SGND provides 96% voltage programs the phase relationship between CH1 and duty cycle. The maximum duty cycle is derived from an CH2 rising gate signals, as well as the phase relationship internal clock that runs at 12x the programmed switching between CH1 gate signal and CLKOUT. Floating this pin or frequency. As a result, the maximum duty cycle limit DMAX connecting it to either 3V8, or SGND changes the phase is extremely precise. relationship between CH1, CH2 and CLKOUT.
FB (Pin 8/Pin 6/Pin 8):
Error Amplifier Input. The FB pin
PLLFLTR (Pin 12/Pin 10/Pin 12):
PLL Lowpass Filter Input. should be connected through a resistive divider network When synchronizing to an external clock, this pin serves as to VOUT to set the output voltage. the lowpass filter input for the PLL. A series resistor and
FREQ (Pin 5/Pin 3/Pin 5):
A resistor from FREQ to SGND capacitor connected from PLLFLTR to SGND compensate sets the operating frequency. the PLL feedback loop.
GATE1 (Pin 18/Pin 16/Pin 18):
Gate Drive Output. The
RUN (Pin 21/Pin 19/Pin 21):
Run Control Input. A voltage LTC3862 provides a 5V gate drive referenced to PGND to above 1.22V on the pin turns on the IC. Forcing the pin drive a logic-level threshold MOSFET. The gate pin is rated below 1.22V causes the IC to shut down. There is a 0.5µA for an absolute maximum voltage of –0.3V minimum and pull-up current for this pin. Once the RUN pin raises above 6V maximum. 1.22V, an additional 4.5µA pull-up current is added to the pin for programmable hysteresis.
GATE2 (Pin 16/Pin 14/Pin 16):
Gate Drive Output. The LTC3862 provides a 5V gate drive referenced to PGND to
SENSE1+ (Pin 23/Pin 21/Pin 23):
Positive Inputs to the drive a logic-level threshold MOSFET. The gate pin is rated Current Comparators. The ITH pin voltage programs the for an absolute maximum voltage of –0.3V minimum and current comparator offset in order to set the peak current 6V maximum. trip threshold. This pin is normally connected to a sense resistor in the source of the power MOSFET. 3862fc For more information www.linear.com/LTC3862 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions (SSOP/QFN/TSSOP) 3V8 (Pin 24/Pin 22/Pin 24):
Output of the Internal 3.8V
INTVCC (Pin 19/Pin 17/Pin 19):
Output of the Internal 5V LDO from INTVCC. Supply pin for the low voltage analog Low Dropout Regulator (LDO). A low ESR 4.7µF (X5R or and digital circuits. A low ESR 1nF ceramic bypass capacitor better) ceramic bypass capacitor should be connected should be connected between 3V8 and SGND, as close between INTVCC and PGND, as close as possible to the IC. as possible to the IC.
ITH (Pin 7/Pin 5/Pin 7):
Error Amplifier Output. The current
BLANK (Pin 3/Pin 1/Pin 3):
Blanking Time. Floating this comparator trip threshold increases with the ITH control pin provides a nominal minimum on-time of 260ns. Con- voltage. The ITH pin is also used for compensating the necting this pin to 3V8 provides a minimum on-time of control loop of the converter. 340ns, while connecting it to SGND provides a minimum
PGND (Pin 17/Pin 15, Exposed Pad Pin 25/Pin 17,
on-time of 180ns.
Exposed Pad Pin 25):
Power Ground. Connect this pin
CLKOUT (Pin 10/Pin 8/Pin 10):
Digital Output Used for close to the sources of the power MOSFETs. PGND should Daisy-Chaining Multiple LTC3862 ICs in Multi-Phase also be connected to the negative terminals of VIN and Systems. The PHASEMODE pin voltage controls the INTVCC bypass capacitors. PGND is electrically isolated relationship between CH1 and CH2 as well as between from the SGND pin. The Exposed Pad of the FE and QFN CH1 and CLKOUT. packages is connected to PGND and must be soldered
D
to PCB ground for electrical contact and rated thermal
MAX (Pin 1/Pin 23/Pin 1):
Maximum Duty Cycle. This pin programs the maximum duty cycle. Floating this pin pro- performance. vides 84% duty cycle. Connecting this pin to 3V8 provides
PHASEMODE (Pin 4/Pin 2/Pin 4):
The PHASEMODE pin 75% duty cycle, while connecting it to SGND provides 96% voltage programs the phase relationship between CH1 and duty cycle. The maximum duty cycle is derived from an CH2 rising gate signals, as well as the phase relationship internal clock that runs at 12x the programmed switching between CH1 gate signal and CLKOUT. Floating this pin or frequency. As a result, the maximum duty cycle limit DMAX connecting it to either 3V8, or SGND changes the phase is extremely precise. relationship between CH1, CH2 and CLKOUT.
FB (Pin 8/Pin 6/Pin 8):
Error Amplifier Input. The FB pin
PLLFLTR (Pin 12/Pin 10/Pin 12):
PLL Lowpass Filter Input. should be connected through a resistive divider network When synchronizing to an external clock, this pin serves as to VOUT to set the output voltage. the lowpass filter input for the PLL. A series resistor and
FREQ (Pin 5/Pin 3/Pin 5):
A resistor from FREQ to SGND capacitor connected from PLLFLTR to SGND compensate sets the operating frequency. the PLL feedback loop.
GATE1 (Pin 18/Pin 16/Pin 18):
Gate Drive Output. The
RUN (Pin 21/Pin 19/Pin 21):
Run Control Input. A voltage LTC3862 provides a 5V gate drive referenced to PGND to above 1.22V on the pin turns on the IC. Forcing the pin drive a logic-level threshold MOSFET. The gate pin is rated below 1.22V causes the IC to shut down. There is a 0.5µA for an absolute maximum voltage of –0.3V minimum and pull-up current for this pin. Once the RUN pin raises above 6V maximum. 1.22V, an additional 4.5µA pull-up current is added to the pin for programmable hysteresis.
GATE2 (Pin 16/Pin 14/Pin 16):
Gate Drive Output. The LTC3862 provides a 5V gate drive referenced to PGND to
SENSE1+ (Pin 23/Pin 21/Pin 23):
Positive Inputs to the drive a logic-level threshold MOSFET. The gate pin is rated Current Comparators. The ITH pin voltage programs the for an absolute maximum voltage of –0.3V minimum and current comparator offset in order to set the peak current 6V maximum. trip threshold. This pin is normally connected to a sense resistor in the source of the power MOSFET. 3862fc For more information www.linear.com/LTC3862 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts