Datasheet LTC3835-1 (Analog Devices) - 8

LTC3835-1
PIN FUNCTIONS (DHC Package/GN Package) RUN (Pin 13/Pin 13):
Digital Run Control Input for Input. When an external clock is applied to this pin, the Controller. Forcing this pin below 0.7V shuts down all phase-locked loop will force the rising TG signal to be controller functions, reducing the quiescent current that synchronized with the rising edge of the external clock. In the LTC3835-1 draws to approximately 10μA. this case, an R-C fi lter must be connected to the PLLLPF pin. When not synchronizing to an external clock, this input
SENSE– (Pin 14/Pin 14):
The (–) Input to the Differential determines how the LTC3835-1 operates at light loads. Current Comparator. Pulling this pin below 0.7V selects Burst Mode operation.
SENSE+ (Pin 15/Pin 15):
The (+) Input to the Differential Tying this pin to INTVCC forces continuous inductor current Current Comparator. The ITH pin voltage and controlled operation. Tying this pin to a voltage greater than 0.9V and offsets between the SENSE– and SENSE+ pins in conjunc- less than INTVCC selects pulse-skipping operation. tion with RSENSE set the current trip threshold.
Exposed Pad (Pin 17, DHC Package):
SGND. Must be
PLLIN/MODE (Pin 16/Pin 16):
External Synchronization soldered to PCB. Input to Phase Detector and Forced Continuous Control
FUNCTIONAL DIAGRAM
INTV PLLIN/MODE CC VIN FIN PHASE DET DB BOOST R PLLLPF C LP B TG CLK DROP TOP OUT CIN OSCILLATOR D DET BOT FC C SW LP TOP ON S Q R Q SWITCH INTVCC LOGIC BG INTVCC–0.5V – BOT FC + BURSTEN C PGND OUT B 0.4V + SLEEP V PLLIN/MODE – OUT BURSTEN – 0.8V + SHDN RSENSE L ICMP IR + – – + + – – + 6mV SENSE+ 0.45V 2(VFB) SENSE– SLOPE COMP VFB RB VFB – VIN EA TRACK/SS + 0.80V V R IN A OV + LDO – 0.88V 0.5μA C 5.25V I C TH INTVCC 6V C R C2 C + 1μA INTERNAL SGND SUPPLY TRACK/SS RUN SHDN CSS 3835-1 FD 38351fc 8