Datasheet LTC3832, LTC3832-1 (Analog Devices) - 6

LTC3832/LTC3832-1
W U TYPICAL PERFOR A CE CHARACTERISTICS PVCC Supply Current G1 Rise/Fall Time vs Gate Capacitance vs Gate Capacitance Transient Response
80 200 TA = 25°C TA = 25°C 180 70 160 VOUT 60 50mV/DIV 140 50 120 PVCC1,2 = 12V tf AT PVCC1,2 = 5V 40 100 t I r AT PVCC1,2 = 5V LOAD 80 30 2AV/DIV SUPPLY CURRENT (mA) PVCC1,2 = 5V 60 CC 20 G1 RISE/FALL TIME (ns) PV 40 t 50µs/DIV 3832 G21 10 f AT PVCC1,2 = 12V 20 tr AT PVCC1,2 = 12V 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF) GATE CAPACITANCE AT G1 AND G2 (nF) 3832 G19 3832 G20
U U U PI FU CTIO S (LTC3832/LTC3832-1) G1 (Pin 1/Pin 1):
Top Gate Driver Output. Connect this pin divider to set the output voltage, float SENSE+ and SENSE– to the gate of the upper N-channel MOSFET, Q1. This and connect the external resistor divider to FB. The internal output swings from PGND to PVCC1. It remains low if G2 resistor divider is not included in the LTC3832-1. is high or during shutdown mode.
SHDN (Pin 8/NA):
Shutdown. A TTL compatible low level
PVCC1 (Pin 2/Pin 2):
Power Supply Input for G1. Connect at SHDN for longer than 100µs puts the LTC3832 into this pin to a potential of at least VIN + VGS(ON)(Q1). This shutdown mode. In shutdown, G1 and G2 go low, all potential can be generated using an external supply or internal circuits are disabled and the quiescent current charge pump. drops to 10µA max. A TTL compatible high level at SHDN allows the part to operate normally. This pin also doubles
PGND (Pin 3/Pin 3):
Power Ground. Both drivers return to as an external clock input to synchronize the internal this pin. Connect this pin to a low impedance ground in oscillator with an external clock. The shutdown function is close proximity to the source of Q2. Refer to the Layout disabled in the LTC3832-1. Consideration section for more details on PCB layout techniques. The LTC3832-1 has PGND and GND tied
SS (Pin 9/Pin 5):
Soft-Start. Connect this pin to an external together internally at Pin 3. capacitor, CSS, to implement a soft-start function. If the LTC3832 goes into current limit, C
GND (Pin 4/Pin 3):
Signal Ground. All low power internal SS is discharged to reduce the duty cycle. C circuitry returns to this pin. To minimize regulation errors SS must be selected such that during power-up, the current through Q1 will not exceed due to ground currents, connect GND to PGND right at the the current limit level. LTC3832.
COMP (Pin 10/Pin 6):
External Compensation. This pin
SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4):
These three internally connects to the output of the error amplifier and pins connect to the internal resistor divider and input of the input of the PWM comparator. Use a RC + C network at this error amplifier. To use the internal divider to set the output pin to compensate the feedback loop to provide optimum voltage to 2.5V, connect SENSE+ to the positive terminal transient response. of the output capacitor and SENSE– to the negative termi- nal. FB should be left floating. To use an external resistor sn3832 3832fs 6