Datasheet LTC3830, LTC3830-1 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation |
| Páginas / Página | 24 / 6 — TYPICAL PERFOR A CE CHARACTERISTICS. PVCC Supply Current. G1 Rise/Fall … |
| Formato / tamaño de archivo | PDF / 277 Kb |
| Idioma del documento | Inglés |
TYPICAL PERFOR A CE CHARACTERISTICS. PVCC Supply Current. G1 Rise/Fall Time. vs Gate Capacitance. Transient Response
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LTC3830/LTC3830-1
W U TYPICAL PERFOR A CE CHARACTERISTICS PVCC Supply Current G1 Rise/Fall Time vs Gate Capacitance vs Gate Capacitance Transient Response
50 200 TA = 25°C TA = 25°C 180 40 160 VOUT PV 50mV/DIV CC1,2 = 12V 140 30 120 tf AT PVCC1,2 = 5V 100 tr AT PVCC1,2 = 5V ILOAD 20 80 2AV/DIV PV SUPPLY CURRENT (mA) CC1,2 = 5V 60 CC G1 RISE/FALL TIME (ns) PV 10 40 t 50µs/DIV f AT PVCC1,2 = 12V 3830 G22.tif 20 tr AT PVCC1,2 = 12V 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF) GATE CAPACITANCE AT G1 AND G2 (nF) 3830 G20 3830 G21
U U U PI FU CTIO S (16-Lead LTC3830/8-Lead LTC3830/LTC3830-1) G1 (Pin 1/Pin 1/Pin 1):
Top Gate Driver Output. Connect resistor divider to set the output voltage, float SENSE+ and this pin to the gate of the upper N-channel MOSFET, Q1. SENSE– and connect the external resistor divider to FB. This output swings from PGND to PVCC1. It remains low if The internal resistor divider is not included in the LTC3830-1 G2 is high or during shutdown mode. and the 8-lead LTC3830.
PVCC1 (Pin 2/Pin 2/Pin 2):
Power Supply Input for G1.
SHDN (Pin 8/Pin 5/NA):
Shutdown. A TTL compatible low Connect this pin to a potential of at least VIN + VGS(ON)(Q1). level at SHDN for longer than 100µs puts the LTC3830 into This potential can be generated using an external supply or shutdown mode. In shutdown, G1 and G2 go low, all charge pump. internal circuits are disabled and the quiescent current drops to 10
PGND (Pin 3/Pin 3/Pin 3):
Power Ground. Both drivers µA max. A TTL compatible high level at SHDN allows the part to operate normally. This pin also doubles return to this pin. Connect this pin to a low impedance as an external clock input to synchronize the internal ground in close proximity to the source of Q2. Refer to the oscillator with an external clock. The shutdown function is Layout Consideration section for more details on PCB disabled in the LTC3830-1. layout techniques. The LTC3830-1 and the 8-lead LTC3830 have PGND and GND tied together internally at Pin 3.
SS (Pin 9/NA/Pin 5):
Soft-Start. Connect this pin to an external capacitor, C
GND (Pin 4/Pin 3/Pin 3):
Signal Ground. All low power SS, to implement a soft-start function. If the LTC3830 goes into current limit, C internal circuitry returns to this pin. To minimize regula- SS is discharged to reduce the duty cycle. C tion errors due to ground currents, connect GND to PGND SS must be selected such that during power-up, the current through Q1 will not exceed right at the LTC3830. the current limit level. The soft-start function is disabled in
SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4/Pin 4):
These the 8-lead LTC3830. three pins connect to the internal resistor divider and input
COMP (Pin 10/Pin 6/Pin 6):
External Compensation. This of the error amplifier. To use the internal divider to set the pin internally connects to the output of the error amplifier output voltage to 3.3V, connect SENSE+ to the positive and input of the PWM comparator. Use a RC + C network terminal of the output capacitor and SENSE– to the nega- at this pin to compensate the feedback loop to provide tive terminal. FB should be left floating. To use an external optimum transient response. 3830fa 6
W U TYPICAL PERFOR A CE CHARACTERISTICS PVCC Supply Current G1 Rise/Fall Time vs Gate Capacitance vs Gate Capacitance Transient Response
50 200 TA = 25°C TA = 25°C 180 40 160 VOUT PV 50mV/DIV CC1,2 = 12V 140 30 120 tf AT PVCC1,2 = 5V 100 tr AT PVCC1,2 = 5V ILOAD 20 80 2AV/DIV PV SUPPLY CURRENT (mA) CC1,2 = 5V 60 CC G1 RISE/FALL TIME (ns) PV 10 40 t 50µs/DIV f AT PVCC1,2 = 12V 3830 G22.tif 20 tr AT PVCC1,2 = 12V 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF) GATE CAPACITANCE AT G1 AND G2 (nF) 3830 G20 3830 G21
U U U PI FU CTIO S (16-Lead LTC3830/8-Lead LTC3830/LTC3830-1) G1 (Pin 1/Pin 1/Pin 1):
Top Gate Driver Output. Connect resistor divider to set the output voltage, float SENSE+ and this pin to the gate of the upper N-channel MOSFET, Q1. SENSE– and connect the external resistor divider to FB. This output swings from PGND to PVCC1. It remains low if The internal resistor divider is not included in the LTC3830-1 G2 is high or during shutdown mode. and the 8-lead LTC3830.
PVCC1 (Pin 2/Pin 2/Pin 2):
Power Supply Input for G1.
SHDN (Pin 8/Pin 5/NA):
Shutdown. A TTL compatible low Connect this pin to a potential of at least VIN + VGS(ON)(Q1). level at SHDN for longer than 100µs puts the LTC3830 into This potential can be generated using an external supply or shutdown mode. In shutdown, G1 and G2 go low, all charge pump. internal circuits are disabled and the quiescent current drops to 10
PGND (Pin 3/Pin 3/Pin 3):
Power Ground. Both drivers µA max. A TTL compatible high level at SHDN allows the part to operate normally. This pin also doubles return to this pin. Connect this pin to a low impedance as an external clock input to synchronize the internal ground in close proximity to the source of Q2. Refer to the oscillator with an external clock. The shutdown function is Layout Consideration section for more details on PCB disabled in the LTC3830-1. layout techniques. The LTC3830-1 and the 8-lead LTC3830 have PGND and GND tied together internally at Pin 3.
SS (Pin 9/NA/Pin 5):
Soft-Start. Connect this pin to an external capacitor, C
GND (Pin 4/Pin 3/Pin 3):
Signal Ground. All low power SS, to implement a soft-start function. If the LTC3830 goes into current limit, C internal circuitry returns to this pin. To minimize regula- SS is discharged to reduce the duty cycle. C tion errors due to ground currents, connect GND to PGND SS must be selected such that during power-up, the current through Q1 will not exceed right at the LTC3830. the current limit level. The soft-start function is disabled in
SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4/Pin 4):
These the 8-lead LTC3830. three pins connect to the internal resistor divider and input
COMP (Pin 10/Pin 6/Pin 6):
External Compensation. This of the error amplifier. To use the internal divider to set the pin internally connects to the output of the error amplifier output voltage to 3.3V, connect SENSE+ to the positive and input of the PWM comparator. Use a RC + C network terminal of the output capacitor and SENSE– to the nega- at this pin to compensate the feedback loop to provide tive terminal. FB should be left floating. To use an external optimum transient response. 3830fa 6