Datasheet LTC3729L-6 (Analog Devices) - 10

LTC3729L-6
U OPERATIO (Refer to Functional Diagram) Main Control Loop Low Current Operation
The LTC3729L-6 uses a constant frequency, current mode The LTC3729L-6 operates in a continuous, PWM control step-down architecture. During normal operation, the top mode. The resulting operation at low output currents MOSFET is turned on each cycle when the oscillator sets optimizes transient response at the expense of substantial the RS latch, and turned off when the main current negative inductor current during the latter part of the comparator, I1, resets the RS latch. The peak inductor period. The level of ripple current is determined by the current at which I1 resets the RS latch is controlled by the inductor value, input voltage, output voltage, and fre- voltage on the ITH pin, which is the output of the error quency of operation. amplifier EA. The differential amplifier, A1, produces a signal equal to the differential voltage sensed across the
Frequency Synchronization
output capacitor but re-references it to the internal signal The phase-locked loop allows the internal oscillator to be ground (SGND) reference. The EAIN pin receives a portion synchronized to an external source via the PLLIN pin. The of this voltage feedback signal at the DIFFOUT pin which output of the phase detector at the PLLFLTR pin is also the is compared to the internal reference voltage by the EA. DC frequency control input of the oscillator that operates When the load current increases, it causes a slight de- over a 260kHz to 550kHz range corresponding to a DC crease in the EAIN pin voltage relative to the 0.6V refer- voltage input from 0V to 2.4V. When locked, the PLL aligns ence, which in turn causes the ITH voltage to increase until the turn on of the top MOSFET to the rising edge of the the average inductor current matches the new load cur- synchronizing signal. When PLLIN is left open, the PLLFLTR rent. After the top MOSFET has turned off, the bottom pin goes low, forcing the oscillator to minimum frequency. MOSFET is turned on for the rest of the period. The internal master oscillator runs at a frequency twelve The top MOSFET drivers are biased from floating boot- times that of each controller’s frequency. The PHASMD strap capacitor CB, which normally is recharged during pin determines the relative phases between the internal each off cycle through an external Schottky diode. When controllers as well as the CLKOUT signal as shown in VIN decreases to a voltage close to VOUT, however, the loop Table␣ 1. The phases tabulated are relative to zero phase may enter dropout and attempt to turn on the top MOSFET being defined as the rising edge of the top gate (TG1) continuously. A dropout detector detects this condition driver output of controller 1. and forces the top MOSFET to turn off for about 400ns every 10th cycle to recharge the bootstrap capacitor.
Table 1. VPHASMD GND OPEN INTVCC
The main control loop is shut down by pulling Pin 1 (RUN/ Controller 2 180° 180° 240° SS) low. Releasing RUN/SS allows an internal 1.2µA CLKOUT 60° 90° 120° current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the The CLKOUT signal can be used to synchronize additional ITH voltage clamped at approximately 30% of its maximum power stages in a multiphase power supply solution value. As CSS continues to charge, ITH is gradually re- feeding a single, high current output or separate outputs. leased allowing normal operation to resume. When the Input capacitance ESR requirements and efficiency losses RUN/SS pin is low, all LTC3729L-6 functions are shut are substantially reduced because the peak current drawn down. If VOUT has not reached 70% of its nominal value from the input capacitor is effectively divided by the when CSS has charged to 4.1V, an overcurrent latchoff can number of phases used and power loss is proportional to be invoked as described in the Applications Information the RMS current squared. A two stage, single output section. voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). sn3729l6 3729l6fs 10