Datasheet LTC3729 (Analog Devices) - 10

LTC3729
OPERATION (Refer to Functional Diagram) Main Control Loop Low Current Operation
The LTC3729 uses a constant frequency, current mode The LTC3729 operates in a continuous, PWM control mode. step‑down architecture. During normal operation, the The resulting operation at low output currents optimizes top MOSFET is turned on each cycle when the oscillator transient response at the expense of substantial negative sets the RS latch, and turned off when the main current inductor current during the latter part of the period. The level comparator, I1, resets the RS latch. The peak inductor of ripple current is determined by the inductor value, input current at which I1 resets the RS latch is controlled by voltage, output voltage, and frequency of operation. the voltage on the ITH pin, which is the output of the error amplifier EA. The differential amplifier, A1, produces a
Frequency Synchronization
signal equal to the differential voltage sensed across the The phase‑locked loop allows the internal oscillator to be output capacitor but re‑references it to the internal signal synchronized to an external source via the PLLIN pin. The ground (SGND) reference. The EAIN pin receives a portion output of the phase detector at the PLLFLTR pin is also the of this voltage feedback signal at the DIFFOUT pin which is DC frequency control input of the oscillator that operates over compared to the internal reference voltage by the EA. When a 250kHz to 550kHz range corresponding to a DC voltage the load current increases, it causes a slight decrease in input from 0V to 2.4V. When locked, the PLL aligns the turn the EAIN pin voltage relative to the 0.8V reference, which on of the top MOSFET to the rising edge of the synchronizing in turn causes the ITH voltage to increase until the average signal. When PLLIN is left open, the PLLFLTR pin goes low, inductor current matches the new load current. After the forcing the oscillator to minimum frequency. top MOSFET has turned off, the bottom MOSFET is turned on for the rest of the period. The internal master oscillator runs at a frequency twelve times that of each controller’s frequency. The PHASMD The top MOSFET drivers are biased from floating bootstrap pin determines the relative phases between the internal capacitor CB, which normally is recharged during each controllers as well as the CLKOUT signal as shown in off cycle through an external Schottky diode. When VIN Table 1. The phases tabulated are relative to zero phase decreases to a voltage close to VOUT, however, the loop being defined as the rising edge of the top gate (TG1) may enter dropout and attempt to turn on the top MOSFET driver output of controller 1. continuously. A dropout detector detects this condition and forces the top MOSFET to turn off for about 400ns every
Table 1.
10th cycle to recharge the bootstrap capacitor.
VPHASMD GND OPEN INTVCC
The main control loop is shut down by pulling Pin 1 Controller 2 180° 180° 240° (RUN/SS) low. Releasing RUN/SS allows an internal 1.2µA CLKOUT 60° 90° 120° current source to charge soft‑start capacitor CSS. When The CLKOUT signal can be used to synchronize additional CSS reaches 1.5V, the main control loop is enabled with the power stages in a multiphase power supply solution feeding ITH voltage clamped at approximately 30% of its maximum a single, high current output or separate outputs. Input value. As CSS continues to charge, ITH is gradually released capacitance ESR requirements and efficiency losses are allowing normal operation to resume. When the RUN/SS substantially reduced because the peak current drawn from pin is low, all LTC3729 functions are shut down. If VOUT the input capacitor is effectively divided by the number has not reached 70% of its nominal value when CSS has of phases used and power loss is proportional to the charged to 4.1V, an overcurrent latchoff can be invoked as RMS current squared. A two stage, single output voltage described in the Applications Information section. implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). 3729fb 10 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts