Datasheet LT8714 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Bipolar Output Synchronous Controller with Seamless Four Quadrant Operation |
| Páginas / Página | 36 / 9 — PIN FUNCTIONS FB (Pin 1):. ISN and ISP (Pins 6 and 7):. BIAS (Pin 8):. VC … |
| Formato / tamaño de archivo | PDF / 1.9 Mb |
| Idioma del documento | Inglés |
PIN FUNCTIONS FB (Pin 1):. ISN and ISP (Pins 6 and 7):. BIAS (Pin 8):. VC (Pin 2):. SS (Pin 3):. INTVEE (Pin 9):. TG (Pin 10):
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LT8714
PIN FUNCTIONS FB (Pin 1):
Feedback Pin. For the four quadrant converter,
ISN and ISP (Pins 6 and 7):
Output Current Sense Nega- tie a resistor from the FB pin to VOUT according to the tive and Positive Input Pins Respectively. Kelvin connect following equation: ISN and ISP pins to a sense resistor to limit the output current. The commanded NFET current will limit the volt- V R OUT – VCTRL FB = 7250Ω • age difference across the sense resistor to 50mV (typical). V CTRL – 0.6065
BIAS (Pin 8):
Top Gate Driver Supply Pin. The BIAS pin
VC (Pin 2):
Error Amplifier Output Pin. Tie external com- sets the top rail for the TG gate driver. Connect this pin to pensation network to this pin. the converter’s input voltage source VIN and bypass locally.
SS (Pin 3):
Soft-Start Pin. Place a soft-start capacitor here
INTVEE (Pin 9):
6.18V-Below-BIAS Regulator Pin. Must be that is greater than 5× the IMON capacitor. Upon start-up, locally bypassed with a minimum capacitance of 2.2µF to the SS pin will be charged by a (nominally) 260k resistor to BIAS. This pin sets the bottom rail for the TG gate driver. ~2.7V. During an overtemperature or UVLO condition, the The TG gate driver can begin switching when BIAS – INTVEE SS pin will be quickly discharged to reset the part. Once exceeds 3.42V (typical). these conditions are clear, the part will attempt to restart.
TG (Pin 10):
PFET Gate Drive Pin. Low and high levels are
PG (Pin 4):
Power Good Pin. The PG pin functions as an BIAS – INTVEE and BIAS respectively. active high Power Good pin. Power is good when VFB is
BG (Pin 11):
NFET Gate Drive Pin. Low and high levels within ±60mV of VCTRL. A pull-up resistor or some other are GND and INTV form of pull-up network is needed on this pin to use this CC respectively. feature. See the Block Diagram and Applications section
INTVCC (Pin 12):
6.3V Input LDO Regulator Pin. Must be for more information. locally bypassed with a minimum capacitance of 2.2µF to GND. A maximum of 5mA external load can connect
IMON (Pin 5):
Output Current Sense Monitor Output Pin. to the INTV Outputs a voltage that is proportional to the voltage seen CC pin. The undervoltage lockout on INTVCC is 4V (typical). The gate driver, BG, can begin switching across the ISP and ISN pins. when INTVCC exceeds 4V (typical). VIMON = 12.14 • (VISP – ISN + 49.9mV)
VIN (Pin 13):
Input Supply Pin. Must be locally bypassed. Since the voltage across the ISP and ISN pins is AC, a The minimum voltage for the part to operate is 4.5V filtering capacitor is needed on the IMON pin to average out (typical). the ISP and ISN voltage. Recommended capacitor values
CSN and CSP (Pins 14 and 15):
NFET Current Sense range from 10nF to 100nF. A 49.9mV offset is added to Negative and Positive Input Pins Respectively. Kelvin the amplifier, so when the average ISP – ISN voltage is connect these pins to a sense resistor to limit the NFET 0V, the IMON voltage is 606mV. When the average volt- switch current. The maximum positive sense voltage at age across the ISP and ISN pins is 50mV, the IMON pin low duty cycle is 66mV (typical). The maximum negative will output 1.208V. Do not resistively load down this pin. sense voltage at low duty cycles is –32mV (typical). 8714f For more information www.linear.com/LT8714 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Appendix Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS FB (Pin 1):
Feedback Pin. For the four quadrant converter,
ISN and ISP (Pins 6 and 7):
Output Current Sense Nega- tie a resistor from the FB pin to VOUT according to the tive and Positive Input Pins Respectively. Kelvin connect following equation: ISN and ISP pins to a sense resistor to limit the output current. The commanded NFET current will limit the volt- V R OUT – VCTRL FB = 7250Ω • age difference across the sense resistor to 50mV (typical). V CTRL – 0.6065
BIAS (Pin 8):
Top Gate Driver Supply Pin. The BIAS pin
VC (Pin 2):
Error Amplifier Output Pin. Tie external com- sets the top rail for the TG gate driver. Connect this pin to pensation network to this pin. the converter’s input voltage source VIN and bypass locally.
SS (Pin 3):
Soft-Start Pin. Place a soft-start capacitor here
INTVEE (Pin 9):
6.18V-Below-BIAS Regulator Pin. Must be that is greater than 5× the IMON capacitor. Upon start-up, locally bypassed with a minimum capacitance of 2.2µF to the SS pin will be charged by a (nominally) 260k resistor to BIAS. This pin sets the bottom rail for the TG gate driver. ~2.7V. During an overtemperature or UVLO condition, the The TG gate driver can begin switching when BIAS – INTVEE SS pin will be quickly discharged to reset the part. Once exceeds 3.42V (typical). these conditions are clear, the part will attempt to restart.
TG (Pin 10):
PFET Gate Drive Pin. Low and high levels are
PG (Pin 4):
Power Good Pin. The PG pin functions as an BIAS – INTVEE and BIAS respectively. active high Power Good pin. Power is good when VFB is
BG (Pin 11):
NFET Gate Drive Pin. Low and high levels within ±60mV of VCTRL. A pull-up resistor or some other are GND and INTV form of pull-up network is needed on this pin to use this CC respectively. feature. See the Block Diagram and Applications section
INTVCC (Pin 12):
6.3V Input LDO Regulator Pin. Must be for more information. locally bypassed with a minimum capacitance of 2.2µF to GND. A maximum of 5mA external load can connect
IMON (Pin 5):
Output Current Sense Monitor Output Pin. to the INTV Outputs a voltage that is proportional to the voltage seen CC pin. The undervoltage lockout on INTVCC is 4V (typical). The gate driver, BG, can begin switching across the ISP and ISN pins. when INTVCC exceeds 4V (typical). VIMON = 12.14 • (VISP – ISN + 49.9mV)
VIN (Pin 13):
Input Supply Pin. Must be locally bypassed. Since the voltage across the ISP and ISN pins is AC, a The minimum voltage for the part to operate is 4.5V filtering capacitor is needed on the IMON pin to average out (typical). the ISP and ISN voltage. Recommended capacitor values
CSN and CSP (Pins 14 and 15):
NFET Current Sense range from 10nF to 100nF. A 49.9mV offset is added to Negative and Positive Input Pins Respectively. Kelvin the amplifier, so when the average ISP – ISN voltage is connect these pins to a sense resistor to limit the NFET 0V, the IMON voltage is 606mV. When the average volt- switch current. The maximum positive sense voltage at age across the ISP and ISN pins is 50mV, the IMON pin low duty cycle is 66mV (typical). The maximum negative will output 1.208V. Do not resistively load down this pin. sense voltage at low duty cycles is –32mV (typical). 8714f For more information www.linear.com/LT8714 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Appendix Typical Applications Package Description Typical Application Related Parts