Datasheet LT8709 (Analog Devices) - 9

LT8709
PIN FUNCTIONS FBY (Pin 1):
Feedback Pin. Its voltage is referred to the pins to average out the ISP and ISN voltage. Recommended GND pin. For a boost, buck-boost, or inverting converter, capacitor values are from 10nF – 100nF. A 51.8mV offset tie a resistor from the FBY pin to VOUT according to the is added to the amplifier such that an average voltage of following equations: 0V on ISP-ISN corresponds to a IMON voltage of 616mV. When the average voltage across the ISP and ISN pins is | V R OUT | –1.234V 50mV, the IMON pin will output ~1.213V. Do not resistively FBY = Negative Output Voltage 83.5µA load down this pin. V
ISN, ISP (Pins 6, 7):
Output Current Sense Negative and R OUT + 15.8mV FBY = Positive Output Voltage Positive Input Pins Respectively. Kelvin connect the ISN 83.9µA and ISP pins to a sense resistor to limit the output cur- See the Applications section for more information. rent. The commanded NFET current will limit the voltage difference across the sense resistor to 50mV.
VC (Pin 2):
Error Amplifier Output Pin. Its voltage is re- ferred to the –V
BIAS (Pin 8):
Additional Input Supply and TG Gate Driver IN pin. Connect an external compensation network between this pin and the –V High Voltage Rail. BIAS is a second positive input sup- IN pin. ply pin in addition to GND and must be locally bypassed
SS (Pin 3):
Soft-Start Pin. Its voltage is referred to the –VIN to –VIN. The BIAS pin sets the top rail for the TG gate pin. Place a soft-start capacitor here that is about 5× greater driver. BIAS must be connected to the converter’s VOUT than the IMON capacitor. Upon start-up, the SS pin will for a negative inverting converter, or INTVCC for a negative be charged by a nominal 260k resistor to ~2.7V. During boost converter, or GND for a negative buck or negative a current overload as seen by ISP-ISN, overtemperature, buck-boost converter. or UVLO condition, the SS pin will be quickly discharged to reset the part. Once these conditions have cleared, the
INTVEE (Pin 9):
6.18V-Below-BIAS Regulator Pin. Must be part will attempt to restart. locally bypassed to BIAS with a minimum capacitance of 2.2µF. This pin sets the bottom rail for the TG gate driver.
PG (Pin 4):
Power Good Indication Pin. Its voltage is The TG gate driver can begin switching when BIAS – referred to the –VIN pin. The PG pin functions as an ac- INTVEE exceeds 3.42V (typical). Connect this pin to –VIN tive high power good pin. Power is good when the FBY for a negative boost converter. pin current is –74.9µA or 75.4µA (~90% of the regulation current), which corresponds to ~90% of the regulation
TG (Pin 10):
PFET Gate Drive Pin. Low and high levels are voltage on V BIAS – INTVEE and BIAS respectively. OUT. For power good indication, there is a 100µs anti-glitch delay. A pull-up resistor or some other
BG (Pin 11):
NFET Gate Drive Pin. Low and high levels form of pull-up network is required on this pin to use the are –VIN and INTVCC respectively. feature. See the Block Diagram and Applications section
INTV
for more information.
CC (Pin 12):
6.3V Dual Input LDO Regulator Pin. Its voltage is referred to the –VIN pin. Must be locally bypassed
IMON (Pin 5):
Output Current Sense Monitor Pin. Its to –VIN with a minimum capacitance of 2.2µF. Logic will voltage is referred to the –VIN pin. Outputs a voltage that choose to run INTVCC from the GND or BIAS pins. A is proportional to the voltage between the ISP and ISN maximum 5mA external load can connect to the INTVCC pins, as given below. pin. The BG gate driver can begin switching when INTVCC V exceeds the 4V (typical) INTVCC undervoltage lockout. IMON = 11.9 • (VISP – ISN + 51.8mV) Since the voltage across the ISP and ISN pins is AC, a
GND (Pin 13):
Positive Input Supply Pin. Must be locally filtering capacitor is needed between the IMON and –V bypassed to –VIN. Can run down to V–VIN as long as BIAS IN –V–VIN > 4.5V. 8709fa For more information www.linear.com/LT8709 9