Datasheet LT3580 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization |
| Páginas / Página | 28 / 5 — TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified. … |
| Formato / tamaño de archivo | PDF / 302 Kb |
| Idioma del documento | Inglés |
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified. SHDN Pin Current. Active/Lockout Threshold
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Versión de texto del documento
LT3580
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified SHDN Pin Current SHDN Pin Current Active/Lockout Threshold
30 300 1.40 –50°C 1.38 25 250 1.36 20°C 1.34 20 200 SHDN RISING 100°C 1.32 15 150 1.30 VOLTAGE (V) 1.28 PIN CURRENT (μA) PIN CURRENT (μA) SHDN FALLING 10 100 SHDN 1.26 SHDN SHDN –50°C 1.24 5 50 100°C 1.22 20°C 0 0 1.20 0 0.5 1 1.5 2 0 5 10 15 20 25 30 –50 0 50 100 SHDN VOLTAGE (V) SHDN VOLTAGE (V) TEMPERATURE (°C) 3580 G10 3580 G11 3580 G12
PIN FUNCTIONS FB (Pin 1):
Positive and Negative Feedback Pin. For a
RT (Pin 6):
Timing Resistor Pin. Adjusts the switching boost or inverting converter, tie a resistor from the FB pin frequency. Place a resistor from this pin to ground to set to VOUT according to the following equations: the frequency to a fixed free running level. Do not float this pin. V − 1.215 ( ) R = OUT ; Boost or SEPIC Converter FB
SS (Pin 7):
Soft-Start Pin. Place a soft-start capacitor here. 83.3 • 10−6 Upon start-up, the SS pin will be charged by a (nominally) V + 5mV ( ) OUT 275k resistor to about 2.2V. R = ; Inverting Converter FB 83.3 • 10−6
SYNC (Pin 8):
To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The
VC (Pin 2):
Error Amplifier Output Pin. Tie external high voltage level of the clock needs to exceed 1.3V, and compensation network to this pin. the low level should be less 0.4V. Drive this pin to less than
V
0.4V to revert to the internal free running clock. See the
IN (Pin 3):
Input Supply Pin. Must be locally bypassed. Applications Information section for more information.
SW (Pin 4):
Switch Pin. This is the collector of the internal NPN Power switch. Minimize the metal trace area connec-
GND (Exposed Pad Pin 9):
Ground. Exposed pad must ted to this pin to minimize EMI. be soldered directly to local ground plane.
SHDN (Pin 5):
Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 1.24V (LT3580E, LT3580I) or 1.22V (LT3580H, LT3580MP) to disable the chip. Drive above 1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP) to activate chip and restart the soft-start sequence. Do not float this pin. 3580fg 5
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified SHDN Pin Current SHDN Pin Current Active/Lockout Threshold
30 300 1.40 –50°C 1.38 25 250 1.36 20°C 1.34 20 200 SHDN RISING 100°C 1.32 15 150 1.30 VOLTAGE (V) 1.28 PIN CURRENT (μA) PIN CURRENT (μA) SHDN FALLING 10 100 SHDN 1.26 SHDN SHDN –50°C 1.24 5 50 100°C 1.22 20°C 0 0 1.20 0 0.5 1 1.5 2 0 5 10 15 20 25 30 –50 0 50 100 SHDN VOLTAGE (V) SHDN VOLTAGE (V) TEMPERATURE (°C) 3580 G10 3580 G11 3580 G12
PIN FUNCTIONS FB (Pin 1):
Positive and Negative Feedback Pin. For a
RT (Pin 6):
Timing Resistor Pin. Adjusts the switching boost or inverting converter, tie a resistor from the FB pin frequency. Place a resistor from this pin to ground to set to VOUT according to the following equations: the frequency to a fixed free running level. Do not float this pin. V − 1.215 ( ) R = OUT ; Boost or SEPIC Converter FB
SS (Pin 7):
Soft-Start Pin. Place a soft-start capacitor here. 83.3 • 10−6 Upon start-up, the SS pin will be charged by a (nominally) V + 5mV ( ) OUT 275k resistor to about 2.2V. R = ; Inverting Converter FB 83.3 • 10−6
SYNC (Pin 8):
To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The
VC (Pin 2):
Error Amplifier Output Pin. Tie external high voltage level of the clock needs to exceed 1.3V, and compensation network to this pin. the low level should be less 0.4V. Drive this pin to less than
V
0.4V to revert to the internal free running clock. See the
IN (Pin 3):
Input Supply Pin. Must be locally bypassed. Applications Information section for more information.
SW (Pin 4):
Switch Pin. This is the collector of the internal NPN Power switch. Minimize the metal trace area connec-
GND (Exposed Pad Pin 9):
Ground. Exposed pad must ted to this pin to minimize EMI. be soldered directly to local ground plane.
SHDN (Pin 5):
Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 1.24V (LT3580E, LT3580I) or 1.22V (LT3580H, LT3580MP) to disable the chip. Drive above 1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP) to activate chip and restart the soft-start sequence. Do not float this pin. 3580fg 5