Datasheet LT1738 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Slew Rate Controlled Ultralow Noise DC/DC Controller |
| Páginas / Página | 20 / 8 — PI FU CTIO S. TEST CIRCUITS. VC (Pin 12):. Figure 1a. Typical Test … |
| Formato / tamaño de archivo | PDF / 260 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. TEST CIRCUITS. VC (Pin 12):. Figure 1a. Typical Test Circuitry Figure 1b. Test Circuit for Slew. BLOCK DIAGRA
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LT1738
U U U PI FU CTIO S TEST CIRCUITS VC (Pin 12):
The compensation pin is used for frequency compensation and current limiting. It is the output of the 20mA 0.9A 5pF error amplifier and the input of the current comparator. 5pF IN5819 IN5819 CAP Loop frequency compensation can be performed with an CAP RC network connected from the VC pin to ground. The GATE Si4450DY voltage on V GATE ZVN3306A C is proportional to the switch peak current. CS The normal range of voltage on this pin is 0.25V to 1.27V. + + 10 2 10 – 0.1 – However, during slope compensation the upper clamp voltage is allowed to increase with the compensation. 1738 F01a 1738 F01b During a short-circuit fault the VC pin will be discharged to
Figure 1a. Typical Test Circuitry Figure 1b. Test Circuit for Slew
ground.
W BLOCK DIAGRA
SHDN VIN V5 R R CSL VSL 14 17 5 15 16 TO DRIVERS + NEGATIVE REGULATOR FEEDBACK – AMP 100k 50k VREG 3 GCL NFB 10 2 CAP – 1 GATE FB 9 ERROR AMP SLEW + CONTROL + 1.25V VC 12 20 PGND – COMP + 4 CS SS 13 + SENSE AMP – S Q FF RT 8 R OSCILLATOR SUB CT 7 6 11 1738 BD SYNC GND 1738fa 8
U U U PI FU CTIO S TEST CIRCUITS VC (Pin 12):
The compensation pin is used for frequency compensation and current limiting. It is the output of the 20mA 0.9A 5pF error amplifier and the input of the current comparator. 5pF IN5819 IN5819 CAP Loop frequency compensation can be performed with an CAP RC network connected from the VC pin to ground. The GATE Si4450DY voltage on V GATE ZVN3306A C is proportional to the switch peak current. CS The normal range of voltage on this pin is 0.25V to 1.27V. + + 10 2 10 – 0.1 – However, during slope compensation the upper clamp voltage is allowed to increase with the compensation. 1738 F01a 1738 F01b During a short-circuit fault the VC pin will be discharged to
Figure 1a. Typical Test Circuitry Figure 1b. Test Circuit for Slew
ground.
W BLOCK DIAGRA
SHDN VIN V5 R R CSL VSL 14 17 5 15 16 TO DRIVERS + NEGATIVE REGULATOR FEEDBACK – AMP 100k 50k VREG 3 GCL NFB 10 2 CAP – 1 GATE FB 9 ERROR AMP SLEW + CONTROL + 1.25V VC 12 20 PGND – COMP + 4 CS SS 13 + SENSE AMP – S Q FF RT 8 R OSCILLATOR SUB CT 7 6 11 1738 BD SYNC GND 1738fa 8