Datasheet Linear Technology LT1613 (Linear Technology) - 4
| Fabricante | Linear Technology |
| Descripción | 1.4MHz, Single Cell DC/DC Converter in 5-Lead SOT-23 |
| Páginas / Página | 12 / 4 — PIN FUNCTIONS. SW (Pin 1):. SHDN (Pin 4):. GND (Pin 2):. VIN (Pin 5):. FB … |
| Revisión | S |
| Formato / tamaño de archivo | PDF / 302 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. SW (Pin 1):. SHDN (Pin 4):. GND (Pin 2):. VIN (Pin 5):. FB (Pin 3):. BLOCK DIAGRAM. OPERATIO
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LT1613
U U U PIN FUNCTIONS SW (Pin 1):
Switch Pin. Connect inductor/diode here.
SHDN (Pin 4):
Shutdown Pin. Tie to 1V or more to enable Minimize trace area at this pin to keep EMI down. device. Ground to shut down.
GND (Pin 2):
Ground. Tie directly to local ground plane.
VIN (Pin 5):
Input Supply Pin. Must be locally bypassed.
FB (Pin 3):
Feedback Pin. Reference voltage is 1.23V. Connect resistive divider tap here. Minimize trace area at FB. Set VOUT according to VOUT = 1.23V(1 + R1/R2).
W BLOCK DIAGRAM
V V IN 5 IN R5 R6 40k 40k V 1 SW OUT + COMPARATOR A1 – R1 g DRIVER (EXTERNAL) m FF – A2 R Q Q3 FB RC RAMP + S Q1 Q2 Σ FB 3 GENERATOR x10 CC + R2 R3 0.15Ω (EXTERNAL) 30k 1.4MHz – OSCILLATOR R4 140k SHDN 4 SHUTDOWN 2 GND 1613 • BD
U OPERATIO
The LT1613 is a current mode, internally compensated, subharmonic oscillations at duty factors greater than fixed frequency step-up switching regulator. Operation 50%) exceeds the VC signal, comparator A2 changes can be best understood by referring to the Block Diagram. state, resetting the flip flop and turning off the switch. Q1 and Q2 form a bandgap reference core whose loop is More power is delivered to the output as switch current is closed around the output of the regulator. The voltage increased. The output voltage, attenuated by external drop across R5 and R6 is low enough such that Q1 and Q2 resistor divider R1 and R2, appears at the FB pin, closing do not saturate, even when VIN is 1V. When there is no the overall loop. Frequency compensation is provided load, FB rises slightly above 1.23V, causing VC (the error internally by RC and CC. Transient response can be opti- amplifier’s output) to decrease. Comparator A2’s output mized by the addition of a phase lead capacitor CPL in stays high, keeping switch Q3 in the off state. As increased parallel with R1 in applications where large value or low output loading causes the FB voltage to decrease, A1’s ESR output capacitors are used. output increases. Switch current is regulated directly on a As the load current is decreased, the switch turns on for a cycle-by-cycle basis by the VC node. The flip flop is set at shorter period each cycle. If the load current is further the beginning of each switch cycle, turning on the switch. decreased, the converter will skip cycles to maintain When the summation of a signal representing switch output voltage regulation. current and a ramp generator (introduced to avoid 4
U U U PIN FUNCTIONS SW (Pin 1):
Switch Pin. Connect inductor/diode here.
SHDN (Pin 4):
Shutdown Pin. Tie to 1V or more to enable Minimize trace area at this pin to keep EMI down. device. Ground to shut down.
GND (Pin 2):
Ground. Tie directly to local ground plane.
VIN (Pin 5):
Input Supply Pin. Must be locally bypassed.
FB (Pin 3):
Feedback Pin. Reference voltage is 1.23V. Connect resistive divider tap here. Minimize trace area at FB. Set VOUT according to VOUT = 1.23V(1 + R1/R2).
W BLOCK DIAGRAM
V V IN 5 IN R5 R6 40k 40k V 1 SW OUT + COMPARATOR A1 – R1 g DRIVER (EXTERNAL) m FF – A2 R Q Q3 FB RC RAMP + S Q1 Q2 Σ FB 3 GENERATOR x10 CC + R2 R3 0.15Ω (EXTERNAL) 30k 1.4MHz – OSCILLATOR R4 140k SHDN 4 SHUTDOWN 2 GND 1613 • BD
U OPERATIO
The LT1613 is a current mode, internally compensated, subharmonic oscillations at duty factors greater than fixed frequency step-up switching regulator. Operation 50%) exceeds the VC signal, comparator A2 changes can be best understood by referring to the Block Diagram. state, resetting the flip flop and turning off the switch. Q1 and Q2 form a bandgap reference core whose loop is More power is delivered to the output as switch current is closed around the output of the regulator. The voltage increased. The output voltage, attenuated by external drop across R5 and R6 is low enough such that Q1 and Q2 resistor divider R1 and R2, appears at the FB pin, closing do not saturate, even when VIN is 1V. When there is no the overall loop. Frequency compensation is provided load, FB rises slightly above 1.23V, causing VC (the error internally by RC and CC. Transient response can be opti- amplifier’s output) to decrease. Comparator A2’s output mized by the addition of a phase lead capacitor CPL in stays high, keeping switch Q3 in the off state. As increased parallel with R1 in applications where large value or low output loading causes the FB voltage to decrease, A1’s ESR output capacitors are used. output increases. Switch current is regulated directly on a As the load current is decreased, the switch turns on for a cycle-by-cycle basis by the VC node. The flip flop is set at shorter period each cycle. If the load current is further the beginning of each switch cycle, turning on the switch. decreased, the converter will skip cycles to maintain When the summation of a signal representing switch output voltage regulation. current and a ramp generator (introduced to avoid 4