Datasheet LT1372, LT1377 (Analog Devices) - 7

LT1372/LT1377
U U W U APPLICATIO S I FOR ATIO
Positive fixed voltage versions are available (consult
Shutdown and Synchronization
Linear Technology marketing). The dual function S/S pin provides easy shutdown and
Negative Output Voltage Setting
synchronization. It is logic level compatible and can be pulled high, tied to VIN or left floating for normal operation. The LT1372/LT1377 develops a – 2.49V reference (VNFR) A logic low on the S/S pin activates shutdown, reducing from the NFB pin to ground. Output voltage is set by the part’s supply current to 12µA. Typical synchronization connecting the NFB pin to an output resistor divider range is from 1.05 to 1.8 times the part’s natural switching (Figure 2). The – 30µA NFB pin bias current (INFB) can frequency, but is only guaranteed between 600kHz and cause output voltage errors and should not be ignored. 800kHz (LT1372) or 1.2MHz and 1.6MHz (LT1377). At This has been accounted for in the formula in Figure 2. The start-up, the synchronization signal should not be applied suggested value for R2 is 2.49k. The FB pin is normally left until the feedback pin is above the frequency shift voltage open for negative output application. See Dual Polarity of 0.7V. If the NFB pin is used, synchronization should not Output Voltage Sensing for limitatins on FB pin loading be applied until the NFB pin is more negative than – 1.4V. when using the NFB pin. A 12µs resetable shutdown delay network guarantees the –VOUT part will not go into shutdown while receiving a synchro- R1 –V ( R2) OUT = VNFB 1 + + INFB (R1) nization signal. R1 INFB NFB Caution should be used when synchronizing above 700kHz PIN VOUT– 2.49 R2 R1 = (LT1372) or 1.4MHz (LT1377) because at higher sync 2.49 –6 ( R2 ) ( ) V + 30 × 10 NFR frequencies the amplitude of the internal slope compensa- LT1372 • F02 tion used to prevent subharmonic switching is reduced.
Figure 2. Negative Output Resistor Divider
This type of subharmonic switching only occurs when the duty cycle of the switch is above 50%. Higher inductor values will tend to eliminate problems.
Dual Polarity Output Voltage Sensing
Certain applications benefit from sensing both positive
Thermal Considerations
and negative output voltages. One example is the “Dual Care should be taken to ensure that the worst-case input Output Flyback Converter with Overvoltage Protection” voltage and load current conditions do not cause exces- circuit shown in the Typical Applications section. Each sive die temperatures. The packages are rated at 120°C/W output voltage resistor divider is individually set as de- for SO (S8) and 130°C/W for PDIP (N8). scribed above. When both the FB and NFB pins are used, the LT1372/LT1377 acts to prevent either output from Average supply current (including driver current) is: going beyond its set output voltage. For example in this IIN = 4mA + DC (ISW/60 + ISW × 0.004) application, if the positive output were more heavily loaded ISW = switch current than the negative, the negative output would be greater and would regulate at the desired set-point voltage. The DC = switch duty cycle positive output would sag slightly below its set-point Switch power dissipation is given by: voltage. This technique prevents either output from going unregulated high at no load. Please note that the load on PSW = (ISW)2 × RSW × DC the FB pin should not exceed 250µA when the NFB pin is RSW = output switch “On” resistance used. This situation occurs when the resistor dividers are Total power dissipation of the die is the sum of supply used at both FB and NFB. True load on FB is not the full current times supply voltage plus switch power: divider current unless the positive output is shorted to ground. See Dual Output Flyback Converter application. PD(TOTAL) = (IIN × VIN) + PSW 7