Datasheet LT3011 (Analog Devices) - 8

LT3011
PIN FUNCTIONS (DFN/MSOP) OUT (Pin 1/Pin 2):
Output. The output supplies power to
CT (Pin 6/Pin 7):
Timing Capacitor. The CT pin allows the the load. A minimum output capacitor of 1μF is required use of a small capacitor to delay the timing between the to prevent oscillations. Larger capacitors will be required point where the output crosses the PWRGD threshold and for applications with large transient loads to limit peak the PWRGD fl ag changes to a high impedance state. Cur- voltage transients. See the Applications Information rent out of this pin during the charging phase is 3μA. The section for more information on output capacitance and voltage difference between the PWRGD low and PWRGD reverse output characteristics. high states is 1.67V (see the Applications Information section).
ADJ (Pin 2/Pin 3):
Adjust. This is the input to the error amplifi er. This pin is internally clamped to ±7V. It has a
SHDN (Pin 8/Pin 9):
Shutdown. The SHDN pin is used bias current of 30nA which fl ows into the pin (see the to put the LT3011 into a low power shutdown state. The curve labeled ADJ Pin Bias Current vs Temperature in the output will be off when the SHDN pin is pulled low. The Typical Performance Characteristics section). The ADJ SHDN pin can be driven either by 5V logic or open-collector pin voltage is 1.24V referenced to ground, and the output logic with a pull-up resistor. The pull-up resistor is only voltage range is 1.24V to 60V. required to supply the pull-up current of the open-collec- tor gate, normally several microamperes. If unused, the
GND (Pins 3, 11/Pins 4, 13):
Ground. The exposed back- SHDN pin must be tied to a logic high or V side of the package (Pin 11/Pin 13) is an electrical connec- IN. tion for GND. As such, to ensure optimum device opera-
IN (Pin 10/Pin 11):
Input. Power is supplied to the device tion and thermal performance, the Exposed Pad must be through the IN pin. A bypass capacitor is required on this connected directly to Pin 3/Pin 4 on the PC board. pin if the device is more than six inches away from the main input fi lter capacitor. In general, the output imped-
NC (Pins 4, 7, 9/Pins 1, 5, 8, 10, 12):
No Connection. ance of a battery rises with frequency, so it is advisable to These pins have no internal connection. Connecting NC include a bypass capacitor in battery-powered circuits. A pins to a copper area for heat dissipation provides a small bypass capacitor in the range of 1μF to 10μF is suffi cient. improvement in thermal performance. The LT3011 is designed to withstand reverse voltages
PWRGD (Pin 5/Pin 6):
Power Good. The PWRGD fl ag is on the IN pin with respect to ground and the OUT pin. In an open-collector fl ag to indicate that the output voltage the case of a reverse input voltage, which can occur if a has increased above 90% of the nominal output voltage. battery is plugged in backwards, the LT3011 will act as if There is no internal pull-up on this pin; a pull-up resistor there is a diode in series with its input. There will be no must be used. The PWRGD pin will change state from an reverse current fl ow into the LT3011 and no reverse volt- open-collector pull-down to high impedance after both age will appear at the load. The device will protect both the output is above 90% of the nominal voltage and the itself and the load. capacitor on the CT pin has charged through a 1.67V dif-
Exposed Pad (Pin 11/Pin 13):
Ground. The Exposed Pad ferential. The maximum pull-down current of the PWRGD must be soldered to the PCB. pin in the low state is 50μA. 3011f 8