Datasheet LT1585A, LT1585A-3.3 (Analog Devices) - 9

LT1585A/LT1585A-3.3
U U W U APPLICATIONS INFORMATION Thermal Considerations
tors” 1990 Linear Applications Handbook, Volume I, The LT1585A/LT1585A-3.3 family protects the device Pages RR3-1 to RR3-20. The output connects to the case under overload conditions with internal power and ther- of both the LT1585A and the LT1585A-3.3. mal limiting circuitry. However, for normal continuous For example, using an LT1585ACT-3.3 (TO-220, com- load conditions, do not exceed maximum junction tem- mercial) and assuming: perature ratings. It is important to consider all sources of V thermal resistance from junction-to-ambient. These IN(Max Continuous) = 5.25V (5V + 5%), VOUT = 3.3V, I sources include the junction-to-case resistance, the case- OUT = 5A to-heat sink interface resistance and the heat sink resis- TA = 70°C, θHEAT SINK = 3°C/W tance. Thermal resistance specifications have been devel- θCASE-TO-HEAT SINK = 1°C/W (with Thermal Compound) oped to more accurately reflect device temperature and ensure safe operating temperatures. The Electrical Char- Power dissipation under these conditions is equal to: acteristics section provides a separate thermal resistance PD = (VIN – VOUT)(IOUT) = (5.25 – 3.3)(5) = 9.75W and maximum junction temperature for both the control circuitry and the power transistor. Older regulators, with Junction temperature will be equal to: a single junction-to-case thermal resistance specifica- TJ = TA + PD(θHEAT SINK + θCASE-TO-HEAT SINK + θJC) tion, use an average of the two values provided here and For the Control Section: allow excessive junction temperatures under certain con- ditions of ambient temperature and heat sink resistance. TJ = 70°C + 9.75W (3°C/W + 1°C/W + 0.7°C/W) Calculate the maximum junction temperature for both = 115.8°C sections to ensure that both thermal limits are met. 115.8°C < 125°C = TJMAX (Control Section Commer- cial range) Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. For the Power Transistor: This is the lowest resistance path for heat flow. Proper TJ = 70°C + 9.75W (3°C/W + 1°C/W + 3°C/W) mounting ensures the best thermal flow from this area of = 138.3°C the package to the heat sink. Linear Technology strongly 138.3°C < 150°C = TJMAX (Power Transistor Com- recommends thermal compound at the case-to-heat sink mercial Range) interface. Use a thermally conductive spacer if the case of the device must be electrically isolated and include its In both cases the junction temperature is below the contribution to the total thermal resistance. Please con- maximum rating for the respective sections, ensuring sult “Mounting Considerations for Power Semiconduc- reliable operation. 1585afa 9