Datasheet LTC1390 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 8-Channel Analog Multiplexer with Serial Interface |
| Páginas / Página | 8 / 6 — APPLICATIO S I FOR ATIO. Table 1. Logic Table for Channel Selection. … |
| Revisión | LTC1390: 8-Channel Analog Multiplexer with Serial Interface Data Sheet |
| Formato / tamaño de archivo | PDF / 167 Kb |
| Idioma del documento | Inglés |
APPLICATIO S I FOR ATIO. Table 1. Logic Table for Channel Selection. CHANNEL STATUS. Multiplexer Expansion
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LTC1390
U U W U APPLICATIO S I FOR ATIO
transmission. Table 1 shows the various bit combinations selection or to Data 2 via Buffer 1 for data transfer. Data for channel selection. appears at Data 2 after the fourth rising edge of the clock. When CS is low, Buffer 2 is enabled and Buffer 1 is
Table 1. Logic Table for Channel Selection
disabled, thus digital input data is directly transferred from
CHANNEL STATUS EN B2 B1 B0
Data 2 to Data 1 without any clock delay. All Off 0 X X X S0 1 0 0 0
Multiplexer Expansion
S1 1 0 0 1 S2 1 0 1 0 Several LTC1390s can be daisy-chained to expand the S3 1 0 1 1 number of multiplexer inputs. No additional interface S4 1 1 0 0 ports are required for the expansion. Figure 5 shows two S5 1 1 0 1 LTC1390s connected at their analog outputs to form a 16- S6 1 1 1 0 to-1 multiplexer at the input to an LTC1286 A/D converter. S7 1 1 1 1 VCC VEE
Digital Data Transfer Operation
VCC The block diagram of Figure 3 shows the components 1 16 1 8 contained within the LTC1390 required for digital data S0 V + VREF VCC 2 15 2 7 transfer. Digital data transfer operation can be performed S1 D LTC1390 +IN CLK 3 14 A 3 LTC1286 6 from Data 1 to Data 2 and vice versa as shown in Figure 4. S2 V – –IN DOUT 4 13 When CS is high, Buffer 1 is enabled and Buffer 2 is S3 DATA 2 4 5 ANALOG GND CS 5 12 INPUTS disabled. The digital input data is fed into the 4-bit shift S4 DATA 1 6 11 S5 CS register and then shifted to the MUX switches for channel 7 10 S6 CLK 8 9 S7 GND CLK V 4-BIT SHIFT MUX CC REGISTER SWITCHES 1 16 S0 V + 47k 2 15 S1 D LTC1390 BUFFER 1 DATA 2 3 14 S2 B V – 4 13 S3 DATA 2 ANALOG 5 12 INPUTS S4 DATA 1 DATA CS 6 11 S5 CS CS 7 10 S6 CLK CLK DATA 1 BUFFER 2 8 9 S7 GND LTC1390 • F05 LTC1390 • F03
Figure 5. Daisy-Chaining Two LTC1390s for Expansion Figure 3. Simplified Block Diagram of the Digital Data Transfer Operation
To ensure that only one channel is switched on at any one time, two sets of channel selection bits are needed for Data CLK 1 2 3 4 as shown in Figure 6. The first data sequence is used to switch off one MUX and the second data sequence is used CS to select one channel from the other MUX, or vice versa. Hi-Z In other words, if bit “ENA” is high and bit “ENB” is low, DATA 1 DATA OUT DATA IN one channel of MUX A is switched on and all channels of DATA 2 DATA IN DATA OUT MUX B are switched off. If bit “ENA” is low and bit “ENB” LTC1390 • F04 is high, all channels of MUX A are switched off and one
Figure 4. Digital Data Transfer Operation
channel of MUX B is switched on. sn1390 1390fs 6
U U W U APPLICATIO S I FOR ATIO
transmission. Table 1 shows the various bit combinations selection or to Data 2 via Buffer 1 for data transfer. Data for channel selection. appears at Data 2 after the fourth rising edge of the clock. When CS is low, Buffer 2 is enabled and Buffer 1 is
Table 1. Logic Table for Channel Selection
disabled, thus digital input data is directly transferred from
CHANNEL STATUS EN B2 B1 B0
Data 2 to Data 1 without any clock delay. All Off 0 X X X S0 1 0 0 0
Multiplexer Expansion
S1 1 0 0 1 S2 1 0 1 0 Several LTC1390s can be daisy-chained to expand the S3 1 0 1 1 number of multiplexer inputs. No additional interface S4 1 1 0 0 ports are required for the expansion. Figure 5 shows two S5 1 1 0 1 LTC1390s connected at their analog outputs to form a 16- S6 1 1 1 0 to-1 multiplexer at the input to an LTC1286 A/D converter. S7 1 1 1 1 VCC VEE
Digital Data Transfer Operation
VCC The block diagram of Figure 3 shows the components 1 16 1 8 contained within the LTC1390 required for digital data S0 V + VREF VCC 2 15 2 7 transfer. Digital data transfer operation can be performed S1 D LTC1390 +IN CLK 3 14 A 3 LTC1286 6 from Data 1 to Data 2 and vice versa as shown in Figure 4. S2 V – –IN DOUT 4 13 When CS is high, Buffer 1 is enabled and Buffer 2 is S3 DATA 2 4 5 ANALOG GND CS 5 12 INPUTS disabled. The digital input data is fed into the 4-bit shift S4 DATA 1 6 11 S5 CS register and then shifted to the MUX switches for channel 7 10 S6 CLK 8 9 S7 GND CLK V 4-BIT SHIFT MUX CC REGISTER SWITCHES 1 16 S0 V + 47k 2 15 S1 D LTC1390 BUFFER 1 DATA 2 3 14 S2 B V – 4 13 S3 DATA 2 ANALOG 5 12 INPUTS S4 DATA 1 DATA CS 6 11 S5 CS CS 7 10 S6 CLK CLK DATA 1 BUFFER 2 8 9 S7 GND LTC1390 • F05 LTC1390 • F03
Figure 5. Daisy-Chaining Two LTC1390s for Expansion Figure 3. Simplified Block Diagram of the Digital Data Transfer Operation
To ensure that only one channel is switched on at any one time, two sets of channel selection bits are needed for Data CLK 1 2 3 4 as shown in Figure 6. The first data sequence is used to switch off one MUX and the second data sequence is used CS to select one channel from the other MUX, or vice versa. Hi-Z In other words, if bit “ENA” is high and bit “ENB” is low, DATA 1 DATA OUT DATA IN one channel of MUX A is switched on and all channels of DATA 2 DATA IN DATA OUT MUX B are switched off. If bit “ENA” is low and bit “ENB” LTC1390 • F04 is high, all channels of MUX A are switched off and one
Figure 4. Digital Data Transfer Operation
channel of MUX B is switched on. sn1390 1390fs 6