Datasheet LTM9012 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | Quad 14-Bit, 125Msps ADC with Integrated Drivers |
| Páginas / Página | 28 / 5 — power requireMenTs. The. denotes the specifications which apply over the … |
| Formato / tamaño de archivo | PDF / 2.1 Mb |
| Idioma del documento | Inglés |
power requireMenTs. The. denotes the specifications which apply over the full operating temperature
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LTM9012
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD ADC Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD ADC Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V VCC Amplifier Supply Voltage (Note 10) l 2.7 3.3 3.6 V IVDD ADC Supply Current Sine Wave Input l 298 320 mA IOVDD ADC Output Supply Current 2-Lane Mode, 1.75mA Mode l 27 31 mA 2-Lane Mode, 3.5mA Mode l 49 54 mA IVCC Amplifier Supply Current l 208 224 mA PDISS 2-Lane Mode, 1.75mA Mode l 1271 1473 mW 2-Lane Mode, 3.5mA Mode l 1311 1517 mW PSLEEP 3 mW PNAP 85 mW PDIFFCLK Power Decrease with Single-Ended 20 mW Encode Mode Enabled
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10, Note 11) l 5 125 MHz tENCL ENC Low Time (Note 9) Duty Cycle Stabilizer Off l 3.8 4 100 ns Duty Cycle Stabilizer On l 2 4 100 ns tENCH ENC High Time (Note 9) Duty Cycle Stabilizer Off l 3.8 4 100 ns Duty Cycle Stabilizer On l 2 4 100 ns tAP Sample-and-Hold 0 ns Acquisition Delay Time
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 1/(8•fS) sec 2-Lanes, 14-Bit Serialization 1/(7•fS) sec 2-Lanes, 12-Bit Serialization 1/(6•fS) sec 1-Lane, 16-Bit Serialization 1/(16•fS) sec 1-Lane, 14-Bit Serialization 1/(14•fS) sec 1-Lane, 12-Bit Serialization 1/(12•fS) sec tFRAME FR to DCO Delay (Note 9) l 0.35•tSER 0.5•tSER 0.65•tSER sec tDATA DATA to DCO Delay (Note 9) l 0.35•tSER 0.5•tSER 0.65•tSER sec tPD Propagation Delay (Note 9) l 0.7n + 2•tSER 1.1n + 2•tSER 1.5n + 2•tSER sec tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles
SPI Port Timing (Note 9)
tSCK SCK Period Write Mode l 40 ns Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 9012fa For more information www.linear.com/LTM9012 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Block Diagram Applications Information Typical Application Package Description Revision History Typical Application Related Parts
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD ADC Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD ADC Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V VCC Amplifier Supply Voltage (Note 10) l 2.7 3.3 3.6 V IVDD ADC Supply Current Sine Wave Input l 298 320 mA IOVDD ADC Output Supply Current 2-Lane Mode, 1.75mA Mode l 27 31 mA 2-Lane Mode, 3.5mA Mode l 49 54 mA IVCC Amplifier Supply Current l 208 224 mA PDISS 2-Lane Mode, 1.75mA Mode l 1271 1473 mW 2-Lane Mode, 3.5mA Mode l 1311 1517 mW PSLEEP 3 mW PNAP 85 mW PDIFFCLK Power Decrease with Single-Ended 20 mW Encode Mode Enabled
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10, Note 11) l 5 125 MHz tENCL ENC Low Time (Note 9) Duty Cycle Stabilizer Off l 3.8 4 100 ns Duty Cycle Stabilizer On l 2 4 100 ns tENCH ENC High Time (Note 9) Duty Cycle Stabilizer Off l 3.8 4 100 ns Duty Cycle Stabilizer On l 2 4 100 ns tAP Sample-and-Hold 0 ns Acquisition Delay Time
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 1/(8•fS) sec 2-Lanes, 14-Bit Serialization 1/(7•fS) sec 2-Lanes, 12-Bit Serialization 1/(6•fS) sec 1-Lane, 16-Bit Serialization 1/(16•fS) sec 1-Lane, 14-Bit Serialization 1/(14•fS) sec 1-Lane, 12-Bit Serialization 1/(12•fS) sec tFRAME FR to DCO Delay (Note 9) l 0.35•tSER 0.5•tSER 0.65•tSER sec tDATA DATA to DCO Delay (Note 9) l 0.35•tSER 0.5•tSER 0.65•tSER sec tPD Propagation Delay (Note 9) l 0.7n + 2•tSER 1.1n + 2•tSER 1.5n + 2•tSER sec tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles
SPI Port Timing (Note 9)
tSCK SCK Period Write Mode l 40 ns Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 9012fa For more information www.linear.com/LTM9012 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Block Diagram Applications Information Typical Application Package Description Revision History Typical Application Related Parts