Datasheet LTC2471, LTC2473 (Analog Devices) - 9

LTC2471/LTC2473
applicaTions inForMaTion Ease of Use I2C INTERFACE
The LTC2471/LTC2473 data output has no latency, filter The LTC2471/LTC2473 communicate through an I2C in- settling delay, or redundant results associated with the terface. The I2C interface is a 2-wire open-drain interface conversion cycle. There is a one-to-one correspondence supporting multiple devices and masters on a single bus. between the conversion and the output data. Therefore, The connected devices can only pull the data line (SDA) multiplexing multiple analog input voltages requires no LOW and can never drive it HIGH. SDA must be externally special actions. connected to the supply through a pull-up resistor. When The LTC2471/LTC2473 include a proprietary input sampling the data line is free, it is HIGH. Data on the I2C bus can scheme that reduces the average input current by several be transferred at rates up to 100kbits/s in the standard orders of magnitude when compared to traditional delta- mode and up to 400kbits/s in the fast mode. sigma architectures. This allows external filter networks Upon entering the DATA INPUT/OUTPUT state, SDA to interface directly to the LTC2471/LTC2473. Since the outputs the sign (D15) of the conversion result. During average input sampling current is 50nA, an external RC this state, the ADC shifts the conversion result serially lowpass filter using 1kΩ and 0.1µF results in <1LSB through the SDA output pin under the control of the SCL additional error. Additionally, there is negligible leakage input pin. There is no latency in generating this data and current between IN+ and IN– (for the LTC2473). the result corresponds to the last completed conversion. A new bit of data appears at the SDA pin following each
Input Voltage Range (LTC2471)
falling edge detected at the SCL input pin and appears Ignoring offset and full-scale errors, the LTC2471 will from MSB to LSB. The user can reliably latch this data on theoretically output an “all zero” digital result when the every rising edge of the external serial clock signal driving input is at ground (a zero scale input) and an “all one” the SCL pin. digital result when the input is at VREF or higher (VREFOUT Each device on the I2C bus is recognized by a unique = 1.25V). In an underrange condition (for all input voltages address stored in that device and can operate either as below zero scale) the converter will generate the output a transmitter or receiver, depending on the function of code 0. In an overrange condition (for all input voltages the device. In addition to transmitters and receivers, greater than VREF) the converter will generate the output devices can also be considered as masters or slaves when code 65535. performing data transfers. A master is the device which
Input Voltage Range (LTC2473)
initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed As detailed in the Output Data Format section, the output by the master are considered a slave. The address of the code is given as INT(32767.5 • (V + – IN – VIN )/VREF + 32767.5. LTC2471/LTC2473 is 0010100 (if A0 is tied to GND) or For (V + – IN – VIN ) ≥ VREF, the output code is clamped at 1010100 (if A0 is tied to VCC). 65535 (all ones). For (V + – IN – VIN ) ≤ –VREF, the output code is clamped at 0 (all zeroes). 24713fb For more information www.linear.com/LTC2471 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts