Datasheet LTC2471, LTC2473 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Selectable 208sps/833sps, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| Páginas / Página | 20 / 7 — block DiagraM. Figure 1. Functional Block Diagram. applicaTions … |
| Formato / tamaño de archivo | PDF / 496 Kb |
| Idioma del documento | Inglés |
block DiagraM. Figure 1. Functional Block Diagram. applicaTions inForMaTion. CONVERTER OPERATION. Converter Operation Cycle
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LTC2471/LTC2473
block DiagraM
1 2 12 REFOUT COMP VCC 3 AO INTERNAL 5 ΔΣ A/D REFERENCE SPI SCL 9 IN+ CONVERTER INTERFACE 6 SDA (IN) DECIMATING – SINC FILTER ΔΣ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 4, 7, 11, 13 DD PACKAGE GND 8 24713 BD 4, 7, 11 MS PACKAGE ( ) PARENTHESIS INDICATE LTC2471
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2471/LTC2473 are low power, delta sigma, analog to digital converters with a simple I2C interface and a user SLEEP/NAP selected 208sps/833sps output rate (see Figure 1). The LTC2473 has a fully differential input while the LTC2471 is single-ended. Both are pin and software compatible. Their NO READ/WRITE operation is composed of three distinct states: CONVERT, ACKNOWLEDGE SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Figure 2). Once the YES conversion is finished, the converter automatically pow- ers down (NAP) or under user control, both the converter DATA INPUT/OUTPUT and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT STOP NO OR YES state. Once all 16-bits are read or an abort is initiated, the READ 16 BITS 24713 F02 device begins a new conversion. The CONVERT state duration is determined by the LTC2471/ LTC2473 conversion time (nominally 4.8ms or 1.2ms
Figure 2. LTC2471/LTC2473 State Transition Diagram
depending on the selected output rate). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. 24713fb For more information www.linear.com/LTC2471 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
block DiagraM
1 2 12 REFOUT COMP VCC 3 AO INTERNAL 5 ΔΣ A/D REFERENCE SPI SCL 9 IN+ CONVERTER INTERFACE 6 SDA (IN) DECIMATING – SINC FILTER ΔΣ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 4, 7, 11, 13 DD PACKAGE GND 8 24713 BD 4, 7, 11 MS PACKAGE ( ) PARENTHESIS INDICATE LTC2471
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2471/LTC2473 are low power, delta sigma, analog to digital converters with a simple I2C interface and a user SLEEP/NAP selected 208sps/833sps output rate (see Figure 1). The LTC2473 has a fully differential input while the LTC2471 is single-ended. Both are pin and software compatible. Their NO READ/WRITE operation is composed of three distinct states: CONVERT, ACKNOWLEDGE SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Figure 2). Once the YES conversion is finished, the converter automatically pow- ers down (NAP) or under user control, both the converter DATA INPUT/OUTPUT and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT STOP NO OR YES state. Once all 16-bits are read or an abort is initiated, the READ 16 BITS 24713 F02 device begins a new conversion. The CONVERT state duration is determined by the LTC2471/ LTC2473 conversion time (nominally 4.8ms or 1.2ms
Figure 2. LTC2471/LTC2473 State Transition Diagram
depending on the selected output rate). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. 24713fb For more information www.linear.com/LTC2471 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts