Datasheet LTC2450-1 (Analog Devices) - 8

LTC2450-1
APPLICATIONS INFORMATION Ease of Use Input Voltage Range
The LTC2450-1 data output has no latency, fi lter settling The ADC is capable of digitizing true rail-to-rail input sig- delay or redundant results associated with the conversion nals. Ignoring offset and full-scale errors, the converter cycle. There is a one-to-one correspondence between the will theoretically output an “all zero” digital result when conversion and the output data. Therefore, multiplexing the input is at ground (a zero scale input) and an “all multiple analog input voltages requires no special ac- one” digital result when the input is at VCC (a full-scale tions. input). In an under-range condition, for all input voltages less than the voltage corresponding to output code 0, the The LTC2450-1 includes a proprietary input sampling converter will generate the output code 0. In an over-range scheme that reduces the average input current several condition, for all input voltages greater than the voltage orders of magnitude as compared to traditional delta corresponding to output code 65535 the converter will sigma architectures. This allows external fi lter networks generate the output code 65535. to interface directly to the LTC2450-1. Since the average input sampling current is 50nA, an external RC lowpass
Output Data Format
fi lter using a 1kΩ and 0.1μF results in <1LSB error. The LTC2450-1 generates a 16-bit direct binary encoded result. It is provided, MSB fi rst, as a 16-bit serial stream
Reference Voltage Range
through the SDO output pin under the control of the SCK The converter uses the power supply voltage (VCC) as the input pin (see Figure 3). positive reference voltage (see Figure 1). Thus, the refer- During the data output operation the CS input pin must ence range is the same as the power supply range, which be pulled low (CS = LOW). The data output process starts extends from 2.7V to 5.5V. The LTC2450-1’s internal noise with the most signifi cant bit of the result being present level is extremely low so the output peak-to-peak noise at the SDO output pin (SDO = D15) once CS goes low. remains well below 1LSB for any reference voltage within A new data bit appears at the SDO output pin following this range. Thus the converter resolution remains at 1LSB every falling edge detected at the SCK input pin. The independent of the reference voltage. INL, offset, and full- output data can be reliably latched by the user using the scale errors vary with the reference voltage as indicated rising edge of SCK. by the Typical Performance Characteristics graphs. These error terms will decrease with an increase in the reference voltage (as the LSB size in μV increases). t3 t t 1 2 CS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D D 1 0 SDO MSB LSB SCK 24501 F03 tKQ tlSCK thSCK
Figure 3. Data Output Timing
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