LTC2446/LTC2447 FUNCTIONAL BLOCK DIAGRAM VCC + INTERNAL VREF01– OSCILLATOR VREF01 • • • REF+ V + AUTOCALIBRATION F REF67 O – AND CONTROL V (INT/EXT) REF67 REF– V + REFG V – REFG CH0 IN+ CH1 DIFFERENTIAL SDI • INPUT/REFERENCE MUX 3RD ORDER • IN– SERIAL SCK • ∆Σ MODULATOR CH7 INTERFACE SDO COM CS DECIMATING FIR GND ADDRESS 24467 F01 Figure 1. Functional Block DiagramTEST CIRCUITS VCC 1.69k SDO SDO 1.69k CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL V 24467 TA03 OH TO Hi-Z V 24467 TA04 OL TO Hi-Z APPLICATIONS INFORMATION POWER UP IN+=CH0, IN–=CH1 CONVERTER OPERATION REF+ = V + REFO1 , REF– = V – REF01 OSR=256,1× MODE Converter Operation Cycle The LTC2446/LTC2447 are multichannel, multireference CONVERT high speed, delta-sigma analog-to-digital converters with an easy to use 3- or 4-wire serial interface (see Figure 1). SLEEP Their operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output/ input (see Figure 2). The 4-wire interface consists of CS = LOW NO AND serial data input (SDI), serial data output (SDO), serial SCK clock (SCK) and chip select (CS). The interface, timing, YES operation cycle and data out format is compatible with CHANNEL SELECT Linear’s entire family of ∆Σ converters. REFERENCE SELECT SPEED SELECT DATA OUTPUT Initially, the LTC2446/LTC2447 perform a conversion. Once 24467 F02 the conversion is complete, the device enters thesleep state. Figure 2. LTC2446/LTC2447 State Transition Diagram 24467fb For more information www.linear.com/LTC2446 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts