Datasheet LTC2444, LTC2445, LTC2448, LTC2449 (Analog Devices) - 9

LTC2444/LTC2445/ LTC2448/LTC2449
applicaTions inForMaTion CONVERTER OPERATION
corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the
Converter Operation Cycle
control of the serial clock (SCK). Data is updated on the The LTC2444/LTC2445/LTC2448/LTC2449 are multi- falling edge of SCK allowing the user to reliably latch data channel, high speed, delta-sigma analog-to-digital convert- on the rising edge of SCK (see Figure 3). The data output ers with an easy to use 3- or 4-wire serial interface (see state is concluded once 32 bits are read out of the ADC Figure 1). Their operation is made up of three states. The or when CS is brought HIGH. The device automatically converter operating cycle begins with the conversion, fol- initiates a new conversion and the cycle repeats. lowed by the low power sleep state and ends with the data Through timing control of the CS, SCK and EXT pins, the output/input (see Figure 2). The 4-wire interface consists LTC2444/LTC2445/LTC2448/LTC2449 offer several flex- of serial data input (SDI), serial data output (SDO), serial ible modes of operation (internal or external SCK). These clock (SCK) and chip select (CS). The interface, timing, various modes do not require programming configuration operation cycle and data out format is compatible with registers; moreover, they do not disturb the cyclic operation Linear’s entire family of ∆Σ converters. described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. POWER UP IN+=CH0, IN–=CH1
Ease of Use
OSR=256,1X MODE The LTC2444/LTC2445/LTC2448/LTC2449 data output CONVERT has no latency, filter settling delay or redundant data associated with the conversion cycle while operating in the 1X mode. There is a one-to-one correspondence SLEEP between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. Speed/ resolution adjustments may be made seamlessly between CS = LOW two conversions without settling errors. AND SCK The LTC2444/LTC2445/LTC2448/LTC2449 perform offset and full-scale calibrations every conversion cycle. This CHANNEL SELECT calibration is transparent to the user and has no effect SPEED SELECT DATA OUTPUT on the cyclic operation described above. The advantage 2444589 F02 of continuous calibration is extreme stability of offset and
Figure 2. LTC2444/LTC2445/LTC2448/LTC2449
full-scale readings with respect to time, supply voltage
State Transition Diagram
change and temperature drift.
Power-Up Sequence
Initially, the LTC2444/LTC2445/LTC2448/LTC2449 per- form a conversion. Once the conversion is complete, the The LTC2444/LTC2445/LTC2448/LTC2449 automatically device enters the sleep state. While in this sleep state, power enter an internal reset state when the power supply volt- consumption is reduced below 10µA. The part remains age VCC drops below approximately 2.2V. This feature in the sleep state as long as CS is HIGH. The conversion guarantees the integrity of the conversion result and of result is held indefinitely in a static shift register while the the serial interface mode selection. converter is in the sleep state. When the VCC voltage rises above this critical threshold, the Once CS is pulled LOW, the device begins outputting the converter creates an internal power-on-reset (POR) signal conversion result. There is no latency in the conversion with a duration of approximately 0.5ms. The POR signal result while operating in the 1x mode. The data output 2444589fc For more information www.linear.com/LTC2444 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Input and Reference Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Pin Functions Functional Block Diagram Test Circuit Applications Information Package Description Revision History Typical Application Related Parts