Datasheet LTC2442 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 24-Bit High Speed 4-Channel ΔΣ ADC with Integrated Amplifier |
| Páginas / Página | 32 / 8 — PIN FUNCTIONS VCC (Pin 29):. F0 (Pin 34):. REF+ (Pin 30), REF– (Pin 31):. … |
| Formato / tamaño de archivo | PDF / 397 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS VCC (Pin 29):. F0 (Pin 34):. REF+ (Pin 30), REF– (Pin 31):. CS (Pin 35):. SDI (Pin 33):. SDO (Pin 36):
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LTC2442
PIN FUNCTIONS VCC (Pin 29):
Positive Supply Voltage. Bypass to GND with
F0 (Pin 34):
Frequency Control Pin. Digital input that con- a 10µF tantalum capacitor in parallel with a 0.1µF ceramic trols the internal conversion clock. When F0 is connected capacitor as close to the part as possible. to VCC or GND, the converter uses its internal oscillator.
REF+ (Pin 30), REF– (Pin 31):
Differential Reference Input.
CS (Pin 35):
Active Low Chip Select. A LOW on this pin The voltage on these pins can have any value between GND enables the SDO digital output and wakes up the ADC. and VCC as long as the reference positive input, REF+, is Following each conversion the ADC automatically enters maintained more positive than the negative reference input, the sleep mode and remains in this state as long as CS is REF–, by at least 0.1V. Bypass to GND with 0.1µF Ceramic HIGH. A LOW-to-HIGH transition on CS during the Data capacitor as close to the part as possible. Output aborts the data transfer and starts a new conversion.
SDI (Pin 33):
Serial Data Input. This pin is used to select
SDO (Pin 36):
Three-State Digital Output. During the data the speed, 1X or 2X mode, resolution and input channel output period, this pin is used as serial data output. When for the next conversion cycle. At initial power up, the de- the chip select CS is HIGH (CS = VCC) the SDO pin is in fault mode of operation is CH0-CH1, OSR of 256 and 1X a high impedance state. During the conversion and sleep mode. The serial data input contains an enable bit which periods, this pin is used as the conversion status output. determines if a new channel/speed is selected. If this bit is The conversion status can be observed by pulling CS LOW. low the following conversion remains at the same speed This signal is HIGH while the conversion is in progress and selected channel. The serial data input is applied to and goes LOW once the conversion is complete. the device under control of the serial clock (SCK) during the data output cycle. The first conversion following a new channel/speed is valid.
FUNCTIONAL BLOCK DIAGRAM
INTERNAL VCC MUXOUTB +INB –INB V+ V– OUTB REF+ ADCINB REF– OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O – AMPB CH0 BUSY CH1 + IN+ DIFFERENTIAL SDI CH2 MUX 3RD ORDER SERIAL SCK + IN– ∆Σ MODULATOR CH3 INTERFACE SDO COM – CS AMPA DECIMATING FIR EXT ADDRESS 2442 F01 MUXOUTA +INA –INA OUTA ADCINA
Figure 1. Functional Block Diagram
2442fb 8 For more information www.linear.com/LTC2442
PIN FUNCTIONS VCC (Pin 29):
Positive Supply Voltage. Bypass to GND with
F0 (Pin 34):
Frequency Control Pin. Digital input that con- a 10µF tantalum capacitor in parallel with a 0.1µF ceramic trols the internal conversion clock. When F0 is connected capacitor as close to the part as possible. to VCC or GND, the converter uses its internal oscillator.
REF+ (Pin 30), REF– (Pin 31):
Differential Reference Input.
CS (Pin 35):
Active Low Chip Select. A LOW on this pin The voltage on these pins can have any value between GND enables the SDO digital output and wakes up the ADC. and VCC as long as the reference positive input, REF+, is Following each conversion the ADC automatically enters maintained more positive than the negative reference input, the sleep mode and remains in this state as long as CS is REF–, by at least 0.1V. Bypass to GND with 0.1µF Ceramic HIGH. A LOW-to-HIGH transition on CS during the Data capacitor as close to the part as possible. Output aborts the data transfer and starts a new conversion.
SDI (Pin 33):
Serial Data Input. This pin is used to select
SDO (Pin 36):
Three-State Digital Output. During the data the speed, 1X or 2X mode, resolution and input channel output period, this pin is used as serial data output. When for the next conversion cycle. At initial power up, the de- the chip select CS is HIGH (CS = VCC) the SDO pin is in fault mode of operation is CH0-CH1, OSR of 256 and 1X a high impedance state. During the conversion and sleep mode. The serial data input contains an enable bit which periods, this pin is used as the conversion status output. determines if a new channel/speed is selected. If this bit is The conversion status can be observed by pulling CS LOW. low the following conversion remains at the same speed This signal is HIGH while the conversion is in progress and selected channel. The serial data input is applied to and goes LOW once the conversion is complete. the device under control of the serial clock (SCK) during the data output cycle. The first conversion following a new channel/speed is valid.
FUNCTIONAL BLOCK DIAGRAM
INTERNAL VCC MUXOUTB +INB –INB V+ V– OUTB REF+ ADCINB REF– OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O – AMPB CH0 BUSY CH1 + IN+ DIFFERENTIAL SDI CH2 MUX 3RD ORDER SERIAL SCK + IN– ∆Σ MODULATOR CH3 INTERFACE SDO COM – CS AMPA DECIMATING FIR EXT ADDRESS 2442 F01 MUXOUTA +INA –INA OUTA ADCINA
Figure 1. Functional Block Diagram
2442fb 8 For more information www.linear.com/LTC2442