Datasheet LTC2436-1 (Analog Devices) - 5

LTC2436-1
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range ● 2.56 2000 kHz tHEO External Oscillator High Period ● 0.25 390 µs tLEO External Oscillator Low Period ● 0.25 390 µs tCONV Conversion Time FO = 0V ● 143.8 146.7 149.6 ms External Oscillator (Note 10) ● 20510/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 9) 17.5 kHz External Oscillator (Notes 9, 10) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 9) ● 45 55 % fESCK External SCK Frequency Range (Note 8) ● 2000 kHz tLESCK External SCK Low Period (Note 8) ● 250 ns tHESCK External SCK High Period (Note 8) ● 250 ns tDOUT_ISCK Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11) ● 1.06 1.09 1.11 ms External Oscillator (Notes 9, 10) ● 152/fEOSC (in kHz) ms tDOUT_ESCK External SCK 19-Bit Data Output Time (Note 8) ● 19/fESCK (in kHz) ms t1 CS ↓ to SDO Low Z ● 0 200 ns t2 CS ↑ to SDO High Z ● 0 200 ns t3 CS ↓ to SCK ↓ (Note 9) ● 0 200 ns t4 CS ↓ to SCK ↑ (Note 8) ● 50 ns tKQMAX SCK ↓ to SDO Valid ● 220 ns tKQMIN SDO Hold After SCK ↓ (Note 5) ● 15 ns t5 SCK Set-Up Before CS ↓ ● 50 ns t6 SCK Hold After CS ↓ ● 50 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the
Note 8:
The converter is in external SCK mode of operation such that life of the device may be impaired. the SCK pin is used as digital input. The frequency of the clock signal
Note 2:
All voltage values are with respect to GND. driving SCK during the data output is fESCK and is expressed in kHz.
Note 3:
V
Note 9:
The converter is in internal SCK mode of operation such that CC = 2.7V to 5.5V unless otherwise specified. V the SCK pin is used as digital output. In this mode of operation the REF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN –, V SCK pin has a total equivalent load capacitance C INCM = (IN+ + IN –)/2, IN+ and IN– are defined as the selected positive LOAD = 20pF. (CH0+ or CH1+) and negative (CH0– or CH1–) input respectively.
Note 10:
The external oscillator is connected to the FO pin. The external
Note 4:
F oscillator frequency, f O pin tied to GND or to an external conversion clock source EOSC, is expressed in kHz. with fEOSC = 139,800Hz unless otherwise specified.
Note 11:
The converter uses the internal oscillator.
Note 5:
Guaranteed by design, not subject to test. FO = 0V.
Note 6:
Integral nonlinearity is defined as the deviation of a code from
Note 12:
800nV RMS noise is independent of VREF. Since the noise a precise analog input voltage. Maximum specifications are limited by performance is limited by the quantization, lowering VREF improves the the LSB step size (V effective resolution. REF/216) and the single shot measurement. Typical specifications are measured from the center of the quantization band.
Note 13:
Guaranteed by design and test correlation.
Note 7:
FO = GND (internal oscillator) or fEOSC = 139,800Hz ±2%
Note 14:
The low sleep mode current is valid only when CS is high. (external oscillator). 24361f 5