Datasheet LTC2411, LTC2411-1 (Analog Devices) - 10

LTC2411/LTC2411-1
PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND is in a high impedance state. During the Conversion and (Pin 6) with a 10µF tantalum capacitor in parallel with Sleep periods, this pin is used as the conversion status 0.1µF ceramic capacitor as close to the part as possible. output. The conversion status can be observed by pulling
REF+ (Pin 2), REF– (Pin 3):
Differential Reference Input. CS LOW. The voltage on these pins can have any value between GND
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal and VCC as long as the reference positive input, REF+, is Serial Clock Operation mode, SCK is used as the digital more positive than the reference negative input, REF–, by output for the internal serial interface clock during the at least 0.1V. Data Output period. In External Serial Clock Operation
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Input. The mode, SCK is used as the digital input for the external se- voltage on these pins can have any value between rial interface clock during the Data Output period. A weak GND – 0.3V and V internal pull-up is automatically activated in Internal Serial CC + 0.3V. Within these limits, the con- verter bipolar input range (V Clock Operation mode. The Serial Clock Operation mode IN = IN+ – IN–) extends from –0.5 • (V is determined by the logic level applied to the SCK pin at REF) to 0.5 • (VREF). Outside this input range, the converter produces unique overrange and underrange power up or during the most recent falling edge of CS. output codes.
FO (Pin 10):
Frequency Control Pin. Digital input that
GND (Pin 6):
Ground. Connect this pin to a ground plane controls the ADC’s notch frequencies and conversion time. through a low impedance connection. For the LTC2411, when the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin the digital filter first null is located at 50Hz. When the FO enables the SDO digital output and wakes up the ADC. pin is connected to GND (FO = 0V), the converter uses its Following each conversion the ADC automatically enters internal oscillator and the digital filter first null is located the Sleep mode and remains in this low power state as at 60Hz. For the LTC2411-1, the converter provides simul- long as CS is HIGH. A LOW-to-HIGH transition on CS taneous 50Hz/60Hz rejection with the FO pin connected to during the Data Output transfer aborts the data transfer GND. When FO is driven by an external clock signal with and starts a new conversion. a frequency fEOSC, the converters use this signal as their
SDO (Pin 8):
Three-State Digital Output. During the Data system clock and the digital filter first null is located at a Output period, this pin is used as the serial data output. frequency fEOSC/2560. When the chip select CS is HIGH (CS = VCC), the SDO pin 2411fa 10 For more information www.linear.com/LTC2411