Datasheet LTC2400 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 24-Bit µPower No Latency ∆Σ™ ADC in SO-8 |
| Páginas / Página | 40 / 8 — TYPICAL PERFOR A CE CHARACTERISTICS. INL vs Output Rate. Resolution vs … |
| Formato / tamaño de archivo | PDF / 481 Kb |
| Idioma del documento | Inglés |
TYPICAL PERFOR A CE CHARACTERISTICS. INL vs Output Rate. Resolution vs Output Rate. PIN FUNCTIONS. VCC (Pin 1):. SDO (Pin 6):
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LTC2400
W U TYPICAL PERFOR A CE CHARACTERISTICS INL vs Output Rate Resolution vs Output Rate
24 24 VCC = 5V VCC = 5V V V 22 REF = 5V 22 REF = 5V TA = 25°C TA = 25°C F F 20 0 = EXTERNAL 20 O = EXTERNAL 18 18 16 16 INL (BITS) 14 14 RESOLUTION (BITS)* 12 12 10 10 LOG(V *RESOLUTION = REF/RMS NOISE) LOG (2) 8 8 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 OUTPUT RATE (Hz) OUTPUT RATE (Hz) 2400 G27 2400 G28
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND
SDO (Pin 6):
Three-State Digital Output. During the data (Pin␣ 4) with a 10µF tantalum capacitor in parallel with output period, this pin is used for serial data output. When 0.1µF ceramic capacitor as close to the part as possible. the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep
VREF (Pin 2):
Reference Input. The reference voltage range periods this pin can be used as a conversion status output. is 0.1V to VCC. The conversion status can be observed by pulling CS LOW.
VIN (Pin 3):
Analog Input. The input voltage range is
SCK (Pin 7):
Bidirectional Digital Clock Pin. In Internal – 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V, the input Serial Clock Operation mode, SCK is used as digital output voltage range may be limited by the pin absolute maxi- for the internal serial interface clock during the data output mum rating of – 0.3V to VCC + 0.3V. period. In External Serial Clock Operation mode, SCK is
GND (Pin 4):
Ground. Shared pin for analog ground, used as digital input for the external serial interface. A digital ground, reference ground and signal ground. Should weak internal pull-up is automatically activated in Internal be connected directly to a ground plane through a mini- Serial Clock Operation mode. The Serial Clock mode is mum length trace or it should be the single-point-ground determined by the level applied to SCK at power up and the in a single point grounding system. falling edge of CS.
CS (Pin 5):
Active LOW Digital Input. A LOW on this pin
FO (Pin 8):
Frequency Control Pin. Digital input that enables the SDO digital output and wakes up the ADC. controls the ADC’s notch frequencies and conversion Following each conversion the ADC automatically enters time. When the FO pin is connected to VCC (FO = VCC), the the Sleep mode and remains in this low power state as converter uses its internal oscillator and the digital filter long as CS is HIGH. A LOW on CS wakes up the ADC. A first null is located at 50Hz. When the FO pin is connected LOW-to-HIGH transition on this pin disables the SDO to GND (FO = OV), the converter uses its internal oscillator digital output. A LOW-to-HIGH transition on CS during the and the digital filter first null is located at 60Hz. When FO Data Output transfer aborts the data transfer and starts a is driven by an external clock signal with a frequency fEOSC, new conversion. the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560. 8
W U TYPICAL PERFOR A CE CHARACTERISTICS INL vs Output Rate Resolution vs Output Rate
24 24 VCC = 5V VCC = 5V V V 22 REF = 5V 22 REF = 5V TA = 25°C TA = 25°C F F 20 0 = EXTERNAL 20 O = EXTERNAL 18 18 16 16 INL (BITS) 14 14 RESOLUTION (BITS)* 12 12 10 10 LOG(V *RESOLUTION = REF/RMS NOISE) LOG (2) 8 8 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 OUTPUT RATE (Hz) OUTPUT RATE (Hz) 2400 G27 2400 G28
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND
SDO (Pin 6):
Three-State Digital Output. During the data (Pin␣ 4) with a 10µF tantalum capacitor in parallel with output period, this pin is used for serial data output. When 0.1µF ceramic capacitor as close to the part as possible. the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep
VREF (Pin 2):
Reference Input. The reference voltage range periods this pin can be used as a conversion status output. is 0.1V to VCC. The conversion status can be observed by pulling CS LOW.
VIN (Pin 3):
Analog Input. The input voltage range is
SCK (Pin 7):
Bidirectional Digital Clock Pin. In Internal – 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V, the input Serial Clock Operation mode, SCK is used as digital output voltage range may be limited by the pin absolute maxi- for the internal serial interface clock during the data output mum rating of – 0.3V to VCC + 0.3V. period. In External Serial Clock Operation mode, SCK is
GND (Pin 4):
Ground. Shared pin for analog ground, used as digital input for the external serial interface. A digital ground, reference ground and signal ground. Should weak internal pull-up is automatically activated in Internal be connected directly to a ground plane through a mini- Serial Clock Operation mode. The Serial Clock mode is mum length trace or it should be the single-point-ground determined by the level applied to SCK at power up and the in a single point grounding system. falling edge of CS.
CS (Pin 5):
Active LOW Digital Input. A LOW on this pin
FO (Pin 8):
Frequency Control Pin. Digital input that enables the SDO digital output and wakes up the ADC. controls the ADC’s notch frequencies and conversion Following each conversion the ADC automatically enters time. When the FO pin is connected to VCC (FO = VCC), the the Sleep mode and remains in this low power state as converter uses its internal oscillator and the digital filter long as CS is HIGH. A LOW on CS wakes up the ADC. A first null is located at 50Hz. When the FO pin is connected LOW-to-HIGH transition on this pin disables the SDO to GND (FO = OV), the converter uses its internal oscillator digital output. A LOW-to-HIGH transition on CS during the and the digital filter first null is located at 60Hz. When FO Data Output transfer aborts the data transfer and starts a is driven by an external clock signal with a frequency fEOSC, new conversion. the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560. 8