Datasheet LTC2393-16 (Analog Devices) - 8

LTC2393-16
PIN FUNCTIONS GND (Pins 1, 5, 7, 20, 35, 41, 44, 48, Exposed Pad D7 (Pin 16):
Data Bit 7. When SER/PAR = 0 this pin is
Pin 49 (QFN Only)):
Ground. All GND pins must be con- Bit 7 of the parallel port data output bus. nected to a solid ground plane. Exposed pad must be
OGND (Pin 17):
Digital Ground for the Input/Output soldered directly to the ground plane. Interface.
AVP (Pins 2, 40, 45, 46, 47):
5V Analog Power Supply.
OVP (Pin 18):
Digital Power Supply for the Input/Output The range of AVP is 4.75V to 5.25V. Bypass AVP to GND Interface. The range for OVP is 1.8V to 5V. Bypass OVP with a good quality 0.1μF and a 10μF ceramic capacitor to OGND with a good quality 4.7μF ceramic capacitor in parallel. close to the pin.
DVP (Pins 3, 19):
5V Digital Power Supply. The range of
D8 (Pin 21):
Data Bit 8. When SER/PAR = 0 this pin is DVP is 4.75V to 5.25V. Bypass DVP to GND with a good Bit 8 of the parallel port data output bus. quality 0.1μF and a 10μF ceramic capacitor in parallel.
D9/SDIN (Pin 22):
Data Bit 9/Serial Data Input. When SER/
SER/PAR (Pin 4):
Serial/Parallel Selection Input. This pin PAR = 0 this pin is Bit 9 of the parallel port data output bus. controls the digital interface. A logic high on this pin se- When SER/PAR = 1, (serial mode) this is the serial data lects the serial interface and a logic low selects the parallel input. SDIN can be used as a data input to daisy chain two interface. In the serial mode the non-active digital outputs or more conversion results into a single SDOUT line. The are high impedance. digital data level on SDIN is output on SDOUT with a delay
OB/2C (Pin 6):
Offset Binary/Two’s Complement Input. of 16 SCLK periods after the start of the read sequence. When OB/2C is high, the digital output is offset binary.
D10/SDOUT (Pin 23):
Data Bit 10/Serial Data Output. When When low, the MSB is inverted resulting in two’s comple- SER/PAR = 0 this pin is Bit 10 of the parallel port data ment output. output bus. When SER/PAR = 1, (serial mode) this is the
BYTESWAP (Pin 8):
BYTESWAP Input. With BYTESWAP serial data output. The conversion result can be clocked low, data will be output with Pin 28 (D15) being the MSB out serially on this pin synchronized to SCLK. The data and Pin 9 (D0) being the LSB. With BYTESWAP high, the is clocked out MSB first on the rising edge of SCLK and upper eight bits and the lower eight bits will be switched. is valid on the falling edge of SCLK. The data format is The MSB is output on Pin 16 and Bit 8 is output on Pin 9. determined by the logic level of OB/2C. Bit 7 is output on Pin 28 and the LSB is output on Pin 21.
D11/SCLK (Pin 24):
Data Bit 11/Serial Clock Input. When
D0 (Pin 9):
Data Bit 0. When SER/PAR = 0 this pin is Bit 0 SER/PAR = 0 this pin is Bit 11 of the parallel port data of the parallel port data output bus. output bus. When SER/PAR = 1, (serial mode) this is the
D1 (Pin 10):
Data Bit 1. When SER/PAR = 0 this pin is serial clock input. Bit 1 of the parallel port data output bus.
D12 (Pin 25):
Data Bit 12. When SER/PAR = 0 this pin is
D2 (Pin 11):
Data Bit 2. When SER/PAR = 0 this pin is Bit 12 of the parallel port data output bus. Bit 2 of the parallel port data output bus.
D13 (Pin 26):
Data Bit 13. When SER/PAR = 0 this pin is
D3 (Pin 12):
Data Bit 3. When SER/PAR = 0 this pin is Bit 13 of the parallel port data output bus. Bit 3 of the parallel port data output bus.
D14 (Pin 27):
Data Bit 14. When SER/PAR = 0 this pin is
D4 (Pin 13):
Data Bit 4. When SER/PAR = 0 this pin is Bit 14 of the parallel port data output bus. Bit 4 of the parallel port data output bus.
D15 (Pin 28):
Data Bit 15. When SER/PAR = 0 this pin is
D5 (Pin 14):
Data Bit 5. When SER/PAR = 0 this pin is Bit 15 of the parallel port data output bus. The data format Bit 5 of the parallel port data output bus. is determined by the logic level of OB/2C.
D6 (Pin 15):
Data Bit 6. When SER/PAR = 0 this pin is Bit 6 of the parallel port data output bus. 239316fa 8